
7534 Group
Rev.3.00 Oct 23, 2006 page 26 of 53
REJ03B0099-0300
Fig. 29 Structure of serial I/O1-related registers (3)
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(USBA: address 0025
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USB PID control register 1
(EP1PID: address 0024
16
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b7 b0
x: any data
b6
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b7
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Clear
b
7
b
0
USB PID control register 0
(EP0PID: address 0023
16
)
Not used (return “1” when read)
Endpoint 0 enable flag
0: Endpoint 0 invalid
1: Endpoint 0 valid
Endpoint 0 PID selection flag
1xxx: IN token interrupt of DATA0/1 is valid
01xx: STALL handshake is valid for IN token
00xx: NAK handshake is valid for IN token
xxx1: STALL handshake is valid for OUT token (Note)
xx10: ACK handshake is valid for OUT token
xx00: NAK handshake is valid for OUT token
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b4, b5, b6
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b7
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Clear
x: any data
Note: In the status stage of the control read transfer, when PID
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