Renesas PROM Programming Adapter PCA7435FPG02 Dokumentacja Pobierz pdf (Strona 14)

7534 Group

Rev.3.00 Oct 23, 2006 page 14 of 53

REJ03B0099-0300

Fig. 14 Block diagram of ports (1)

Data bus

(1) Port P0

Data bus

Direction

Port latch

Pull-up control

To key input interrupt

generating circuit

Data bus

Direction

Port latch

Serial I/O1 mode selection bit (b7)

Serial I/O1 mode selection bit (b6)

Receive enable bit

Serial I/O1 mode selection bit (b7)

Serial I/O1 mode selection bit (b6)

0,P12,P13 input

level selection bit

D- input

D- output

Serial I/O1 input

USB output enable

(internal signal)

USB differential input

D+ input

D+ output

Serial I/O1 output

USB output enable

(internal signal)

Direction

Port latch

(3) Port P11

P-channel output disable bit

(2) Port P10

(4) Port P12

(5) Port P13

Data bus

Direction

0,P12,P13 input

level selection bit

CLK pin selection bit

Port latch

Serial I/O2 clock output

Serial I/O2 clock input

Serial I/O2 clock output

Serial I/O2 clock input

0,P12,P13 input

level selection bit

Data bus

Direction

Signals during the

DATA output action

Port latch

DATA pin selection bit

DATA pin

selection bit

: P1

0, P12, P13, P36, P37 input levels are switched to the CMOS/TTL level by the port P1P3 control register.

Serial I/O1 mode selection bit (b7)

Serial I/O1 mode selection bit (b6)

Serial I/O1 mode selection bit (b7)

Serial I/O1 mode selection bit (b6)

Transmit enable bit

When the TTL level is selected, there is no hysteresis characteristics.

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 55 56

Komentarze do niniejszej Instrukcji

Brak uwag

Renesas PROM Programming Adapter PCA7435FPG02 Dokumentacja Strona 14

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Płyty główne Renesas PROM Programming Adapter PCA7435FPG02