Renesas PROM Programming Adapter PCA7435FPG02 Dokumentacja Pobierz pdf (Strona 12)

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Rev.3.00 Oct 23, 2006 page 12 of 53

REJ03B0099-0300

I/O Ports

[Direction registers] PiD

The I/O ports have direction registers which determine the input/out-

put direction of each pin. Each bit in a direction register corresponds

to one pin, and each pin can be set to be input or output.

When “1” is set to the bit corresponding to a pin, this pin becomes an

output port. When “0” is set to the bit, the pin becomes an input port.

When data is read from a pin set to output, not the value of the pin

itself but the value of port latch is read. Pins set to input are floating,

and permit reading pin values.

If a pin set to input is written to, only the port latch is written to and the

pin remains floating.

[Pull-up control] PULL

By setting the pull-up control register (address 001616), ports P0 and

P3 can exert pull-up control by program. However, pins set to output

are disconnected from this control and cannot exert pull-up control.

[Port P1P3 control] P1P3C

By setting the port P1P3 control register (address 001716), a CMOS

input level or a TTL input level can be selected for ports P10, P12,

P13, P36 and P37 by program.

Then, as for the 36-pin version, set “1” to each bit 6 of the port P3

direction register and port P3 register.

As for the 32-pin version, set “1” to respective bits 5, 6, 7 of the port

P3 direction register and port P3 register.

Fig. 13 Structure of port P1P3 control register

Fig. 12 Structure of pull-up control register

Pull-up control register

(PULL: address 0016

)

pull-up control bit

, P0

pull-up control bit

– P0

pull-up control bit

– P3

pull-up control bit

, P3

pull-up control bit

Note : Pins set to output ports are disconnected from pull-up control.

b7 b0

0: Pull-up off

1: Pull-up on

Initial value: FF

Port P1P3 control register

(P1P3C: address 0017

)

b7 b0

/INT

input level selection bit

0 : CMOS level

1 : TTL level

/INT

input level selection bit

0 : CMOS level

1 : TTL leve

,P1

input level selection bit

0 : CMOS level

1 : TTL level

Not used

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 55 56

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