Renesas PCA7429G02 Informacje Techniczne Strona 43
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Oceniono. / 5. Na podstawie oceny klientów
40
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.6.12 Address Data Communication Format
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8.6.12 Precautions when using multi-master
I
2
C-BUS interface
(1) Read-modify-write instruction
The precautions when the raead-modify-write instruction such as SEB,
CLB etc. is executed for each register of the multi-master I
2
C-BUS
interface are described below.
•I
2
C data shift register (S0)
When executing the read-modify-write instruction for this register
during transfer, data may become a value not intended.
•I
2
C address register (S0D)
When the read-modify-write instruction is executed for this register
at detecting the STOP condition, data may become a value not
intended. It is because hardware changes the read/write bit (RBW)
at the above timing.
•I
2
C status register (S1)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by hardware.
•I
2
C control register (S1D)
When the read-modify-write instruction is executed for this register
at detecting the START condition or at completing the byte transfer,
data may become a value not intended. Because hardware changes
the bit counter (BC0–BC2) at the above timing.
•I
2
C clock control register (S2)
The read-modify-write instruction can be executed for this register.
(2) START condition generating procedure us-
ing multi-master
➀Procedure example (The necessary conditions of the generating
procedure are described as the following ➁ to ➄).
•
•
LDA — (Taking out of slave address value)
SEI (Interrupt disabled)
BBS 5,S1,BUSBUSY
(BB flag confirming and branch process)
BUSFREE:
STA S0 (Writing of slave address value)
LDM #$F0, S1
(Trigger of START condition generating)
CLI (Interrupt enabled)
•
•
BUSBUSY:
CLI (Interrupt enabled)
•
•
➁Use “STA,” “STX” or “STY” of the zero page addressing instruction
for writing the slave address value to the I
2
C data shift register.
➂Use “LDM” instruction for setting trigger of START condition gener-
ating.
➃Write the slave address value of above ➁ and set trigger of START
condition generating of above ➂ continuously shown the above
procedure example.
➄Disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
- To our customers 1
- Renesas Technology Corp 3
- Customer Support Dept 3
- April 1, 2003 3
- To all our customers 3
- M37272E8SP/FP, M37272EFSP 10
- MITSUBISHI MICROCOMPUTERS 69
- Vertical Position Register i 70
- Horizontal Position Register 71
- 8.11.2 Dot Size 72
- 8.11.3 Clock for OSD 73
- Address 00D116 128
- Address 00D216, 00D316 128
- Address 00E516 133
- Address 00E616 133
- Address 00E916 133
- Address 00F516 136
- Address 00F616 136
- Address 00FD16 140
- Address 00FE16 140
- M37273E8SP, M37273EFSP 144
- REVISION DESCRIPTION LIST 145
- DATA SHEET 145
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