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V850E2/MN4 UARTJ Control

R01AN0926EJ0100 Rev.1.00 Page 19 of 30

Feb 07, 2012

Figure 4.11 URTJnCTL1 Register Format (3/3)

Setting example:

URTJnCTL1 = 0x5103; /* Disable BF reception during data reception */

/* Receive/transmit data bit length: 8 bits */

/* No parity */

/* Transmit data output: No inversion, receive data input: No inversion */

/* Transmit data stop bit count: 1 bit */

/* Transfer direction select: LSB first transfer */

/* Transmit interrupt request generated at the end of transmission */

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 32 33

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