Renesas MN4 Dokumentacja

APPLICATION NOTE R01AN0926EJ0100 Rev.1.00 Page 1 of 30 Feb 07, 2012 V850E2/MN4 UARTJ Control Introduction This application note explains how to

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 10 of 30 Feb 07, 2012 4.1.4 Transmit/Receive Control Processing When transmit data is w

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 11 of 30 Feb 07, 2012 4.1.5 Status Interrupt Processing A status interrupt request occu

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 12 of 30 Feb 07, 2012 4.2 Register Setup This section explains how to set up the relevan

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 13 of 30 Feb 07, 2012 4.2.2 UARTJn Control Register 2 (URTJnCTL2) The UARTJnCTL2 regist

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 14 of 30 Feb 07, 2012 Setting example URTJnCTL2 = 0x60D9; /* Assume that PCLK is set

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 15 of 30 Feb 07, 2012 4.2.3 UARTJn Control Register 0 (URTJnCTL0) The UARTJnCTL0 regist

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 16 of 30 Feb 07, 2012 Figure 4.8 URTJnCTL0 Register Format (2/2) Setting examples URT

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 17 of 30 Feb 07, 2012 4.2.4 UARTJn Control Register 1 (URTJnCTL1) The UARTJnCTL1 regist

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 18 of 30 Feb 07, 2012 Figure 4.10 URTJnCTL1 Register Format (2/3)

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 19 of 30 Feb 07, 2012 Figure 4.11 URTJnCTL1 Register Format (3/3) Setting example: U

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 2 of 30 Feb 07, 2012 1. Overview This application note illustrates the usage examples of

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 20 of 30 Feb 07, 2012 4.2.5 FIFO Control Register 0 (URTJnFCTL0) The URTJnFCTL0 registe

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 21 of 30 Feb 07, 2012 4.2.6 FIFO Control Register 1 (URTJnFCTL1) The URTJnFCTL1 registe

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 22 of 30 Feb 07, 2012 4.2.7 UARTJn Status Clear Register 0 (URTJnSTC) The error flags i

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 23 of 30 Feb 07, 2012 4.2.8 FIFO Status Clear Register (URTJnFSTC) The error flags in U

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 24 of 30 Feb 07, 2012 4.3 Function Specifications This section describes the specifica

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 25 of 30 Feb 07, 2012 [Function Name] hbus_initial() [Function] Initializes the AHB

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 26 of 30 Feb 07, 2012 [Function Name] wait() [Function] Waits for a certain number o

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 27 of 30 Feb 07, 2012 4.3.4 Transmit Processing (uartj_transmit.c) [Function Name] urt

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 28 of 30 Feb 07, 2012 4.3.5 Interrupt Processing (interrupt.c) [Function Name] int_urt

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 29 of 30 Feb 07, 2012 [Function Name] int_urtj3ire () [Function] Processes the UARTJ

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 3 of 30 Feb 07, 2012 The basic communication specifications are shown below. Receive I/F

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 30 of 30 Feb 07, 2012 Website and Support Renesas Electronics Website http://www.renesas

A-1 Revision Record Description Rev. Date Page Summary 1.00 Feb 07, 2012 — First edition issued

General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed

Notice1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to chan

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 4 of 30 Feb 07, 2012 1.1 Initialization The general registers and functional pins are in

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 5 of 30 Feb 07, 2012 2. Usage Environment This section provides the circuit diagram and

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 6 of 30 Feb 07, 2012 3. Software This section describes the file organization of the sam

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 7 of 30 Feb 07, 2012 4. Sample Application This section explains how to set up the UARTJ

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 8 of 30 Feb 07, 2012 4.1.2 Receive Interrupt Processing When data is received via the U

V850E2/MN4 UARTJ Control R01AN0926EJ0100 Rev.1.00 Page 9 of 30 Feb 07, 2012 4.1.3 Transmit Interrupt Processing If the fill stage of the trans