Renesas SH7709S Instrukcja Użytkownika Pobierz pdf (Strona 30)

Rev. 1.0, 07/03, page 26 of 38

2.2.4 HM5264165F-B60 (1 Mword × 16 bits × 4 banks)

Bus State Controller (BSC) Settings: When two SDRAMs (HM5264165F-B60) are connected to

area 3 of the SH7727 via a 32-bit bus, the bus state controller (BSC) must be specified as

summarized below. Table 2.9 lists the BSC register settings.

Note that the interface between SDRAM and the SH7727 is performed with bus clock = 66 MHz,

CL = 2, TPC = 2, RCD = 2, TRWL = 1, and TRAS = 4.

1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 43 44

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Renesas SH7709S Instrukcja Użytkownika Strona 30