Renesas User System Interface Cable HS36049ECH61H Instrukcja Użytkownika Pobierz pdf (Strona 13)

Peripherals

On-chip Peripherals: Data Transfer & Memory

Address bus

A15 to A0

External

memory

External

device

(Read)

(Write)

Address bus

Data bus

HWR, LWR

A23 to A0

H8S/2633

DACK

Single-Address Mode (Parallel read and write)

External

memory

External

device

Read (1st cycle)

HWR, LWR

H8S/2633

Dual-Address Mode (Two-cycle read and write)

Address bus

A23 to A0

BUFFER

D15 to D0

Write (2nd cycle)

Data bus

D15 to D0

■ DMA Controller (DMAC)

• Max. of 4 channels can be used

• Dual-address or single-address

mode can be selected

• Supports Single, Burst, Sequential,

Idle and Repeat Transfer modes

• Data can be transferred

in word or byte units

• Activation: internal interrupt,

external request, auto-request

■ Data Transfer Controller (DTC)

• Max. of 85 channels can be used

• Multiple transfers or multiple types of transfers

possible for one activation source

• Supports Single, Burst, Chain and Repeat

Transfer modes

• Data can be transferred in byte or word units

• Activation sources: interrupt and software

Data Transfer

Controller Chain

Transfer Mode

DTC

service

request

Interrupt

controller

On-chip 1KB RAM

Channel n

Interrupt

request

n + 1

n + 2

Source

Memory data

Destination

DMA Register

Source

Serial I/O

Destination

Memory

■ TFT-LCD Direct Drive (ExDMA)

• 16bpp Direct Drive of TFT-LCD panels

• Pixel Clock, V-sync, H-sync, Data Enable

and VCOM driven

• Fully flexible for different panel sizes

and interface specifications

• H8S/2378 drives QVGA, WQVGA panels

– WQVGA (480 x 272) driven at 116Hz

• H8SX/1668 drives VGA and WVGA

– WVGA (800 x 480) driven at 65Hz

•CPU core is lightly loaded during LCD Direct Drive,

leaving CPU core available for other system algorithms

– H8S 6% loaded, H8SX 2% loaded

• Interleaved accesses allow frame buffer update for animation

TFT-LCD Direct Drive (ExDMA)

Pixel Clock

H8S CPU

Processing

Flash

System

Peripherals

H8S/2378 MCU

32KB SRAM • 512KB Flash

QVGA

TFT-LCD

Vsync, Hsync, Enable

Data Bus

256K x 16

SRAM

(Frame Buffer)

RGB

Address Bus

ExDMA

Controller

Timer

(TPU)

EDREQ

RD/

WR/

DMA Controller Block Diagram

■ Data Flash with BGO

• Two blocks of 4KB each of Data Flash

available for storage of non-volatile data

• BGO (Back Ground Operation) allows

Erasing or Programming of Data Flash

while executing application code.

• Erase operation can be suspended automatically to

allow Reading/Programming of User or Data Flash

Time

Erase / Program

Read Read Read Read

Data

Flash

User

Flash

User Flash

(Application)

Data Flash

(Virtual EEPROM)

SRAM

Memory Map

Data Flash with BGO Diagram

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 49 50

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