Renesas Single-Chip Microcomputer M38C89T-ADF Instrukcja Użytkownika Pobierz pdf (Strona 87)

Rev.1.00 May 22 2012

REJ09B0566

4-67

3BLibrary Reference

4.2.7 38BMulti Function Timer Pulse Unit

R_MTU_Create

Description (2/5) [data3]

Configure the counter operation.

[data3]

Configure the IO control registers.

b0:b7 Timer I/O Control Register (TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4)

[data4]

Configure the IO control registers.

b0:b7 Timer I/O Control Register (TIORL_0, TIORL_3, TIORL_4)

[data5]

The register TCNT value.

[data6]

The register TGRA value.

[data7]

The register TGRB value.

[data8]

The register TGRC value

[data9]

The register TGRD value

[data10]

The register TGRE value.

[data11]

The register TGRF value.

[data12]

Configure event interrupt priority value.

[data13]

Configure Over/Underflow interrupt priority value.

Return value

True if all parameters are valid and exclusive; otherwise false.

Category

Multi-function timer pulse unit

Reference

R_MTU_Destroy

Remarks • If an external clock input pin (TCLKx) or I/O pin (TIOCxn) is made active, this function will configure

that pin for input or output and disable other functions on that pin.

• The external clock inputs TCLKA, TCLKB, TCLKC and TCLKD are allocated to pins TCLKA-A,

TCLKB-A, TCLKC-A and TCLKD-A by default.

To select the –B group of pins, use API function R_PFC_Modify(5, 0x08, PDL_PFC_OR) to write 1 to bit

TCLKS in register PFCR5 before calling this function.

Note that these clock inputs are used by channels 0 to 5.

• If the channel is configured for phase counting mode, the counter clock source setting is ignored

• If buffer operation is selected for registers TGRA and TGRC, input capture / output compare is not valid

for register TGRC.

• If buffer operation is selected for registers TGRB and TGRD, input capture / output compare is not valid

for register TGRD.

• If synchronous mode is required, at least two channels must be enabled for synchronous operation.

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