Renesas Single-Chip Microcomputer M38C89T-ADF Instrukcja Użytkownika Pobierz pdf (Strona 101)

Rev.1.00 May 22 2012

REJ09B0566

4-81

Library Reference

4.2.9 40BSerial Communication Interface R_SCI_Create

Description (2/3) • Parity mode

PDL_SCI_PARITY_NONE or

PDL_SCI_PARITY_EVEN or

PDL_SCI_PARITY_ODD

• Stop bit length

PDL_SCI_STOP_1 or

No parity bit, even parity bit or odd parity bit.

PDL_SCI_STOP_2

One or two stop bits.

The option “PDL_SCI_8N1” can be used to select 8-bit data length, no parity and one stop bit.

Options which only apply to Clock Synchronous mode

• Data clock source selection

PDL_SCI_CLK_INT_OUT or

Select the On-chip baud rate generator.

The SCKn pin outputs the bit clock.

PDL_SCI_CLK_EXT Input the clock to the SCKn pin.

Options which apply to Smart Card Interface mode only

• Base clock pulse cycle count

PDL_SCI_BCP_32 or

PDL_SCI_BCP_64 or

PDL_SCI_BCP_93 or

PDL_SCI_BCP_128 or

PDL_SCI_BCP_186 or

PDL_SCI_BCP_256 or

PDL_SCI_BCP_372 or

PDL_SCI_BCP_512

The number of base clock cycles in a 1-bit data transfer period.

• Parity selection

PDL_SCI_PARITY_EVEN or

PDL_SCI_PARITY_ODD

Select even or odd parity bit.

[data3]

This parameter is ignored if the on-chip baud rate generator is not selected.

The format can be either:

• The desired bit rate in bits per second.

The clock source and division values will be calculated and set by this function.

Or one selection from each of the following, using “|” to separate each selection.

• CKS selection

PDL_SCI_PCLK_DIV_1 or

PDL_SCI_PCLK_DIV_4 or

PDL_SCI_PCLK_DIV_16 or

PDL_SCI_PCLK_DIV_64

Select the internal clock signal PCLK ÷ 1, 4, 16 or 64 as the

baud rate generator clock source.

• The BRR register value.

[data4]

The interrupt priority level. Select between 0 (interrupt disabled) and 15 (highest priority).

[data5]

Specify DMA channel number that needs to be assigned to SCI Channel.

Return value

True if all parameters are valid, exclusive and achievable; otherwise false.

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