Renesas Renasas Single-Chip Microcomputer SH7086 Instrukcja Użytkownika Pobierz pdf (Strona 9)

SH7080 Group

A/D Conversion in Single-cycle Scan Mode

REJ06B0699-0100/Rev.1.00 January 2008 Page 7 of 19

4. Principles of Operation

In this sample application, A/D conversion is performed three times in single-cycle scan mode on each of analog input

channels 0 to 3 (AN0 to AN3). Converted data are stored in the on-chip RAM on completion of each round of

conversion on all channels. Figure 3 is a timing diagram of operations in this sample application.

In single-cycle mode, A/D conversion starts when the ADST bit is set to 1. On completion of conversion for the

specified number of channels, the ADST bit is automatically cleared and the ADF bit is automatically set to 1. In this

sample application, three rounds of A/D conversion are performed. The ADF bit is cleared on completion of A/D

conversion. Then ADST bit is set to1 and the remaining two rounds of A/D conversion are performed.

ADST

ADF

First round of

A/D conversion

Third round of

A/D conversion

Second round of

A/D conversion

/D converter

Standby

A/D conversion

Standby

A/D conversion

Standby Standby

A/D conversion

Figure 3 Operational Timing for A/D Conversion

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 20 21

Brak uwag

Renesas Renasas Single-Chip Microcomputer SH7086 Instrukcja Użytkownika Strona 9