Renesas Renasas Single-Chip Microcomputer SH7086 Instrukcja Użytkownika Pobierz pdf (Strona 13)

SH7080 Group

A/D Conversion in Single-cycle Scan Mode

REJ06B0699-0100/Rev.1.00 January 2008 Page 11 of 19

5.4 Register Settings

The registers used in this sample application are described below. The settings below are the values used in this sample

application and differ from the initial values.

5.4.1 Clock Oscillator (CPG) Settings

(1) Frequency Control Register (FPQCR)

Function: Specifies the division ratios for the frequency output by the PLL circuit.

Set value: H'0241

Bit Bit Name Set Value Description

15  0 Reserved

14 to 12 IFC[2:0] 000 Frequency division ratio of the internal clock (Iφ) frequency

000: × 1 (Iφ = 80 MHz for an input clock frequency of 10 MHz)

11 to 9 BFC[2:0] 001 Frequency division ratio of the bus clock (Bφ) frequency

001: × 1/2 (Bφ = 40 MHz for an input clock frequency of 10 MHz)

8 to 6 PFC[2:0] 001 Frequency division ratio of the peripheral clock (Pφ) frequency

001: × 1/2 (Pφ = 40 MHz for an input clock frequency of 10 MHz)

5 to 3 MIFC[2:0] 000

Frequency division ratio of the MTU2S clock (MIφ) frequency

000: × 1 (MIφ = 80 MHz for an input clock frequency of 10 MHz)

2 to 0 MPFC[2:0] 001 Frequency division ratio of the MTU2 clock (MPφ) frequency

001: × 1/2 (MPφ = 40 MHz for an input clock frequency of 10 MHz)

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 19 20 21

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Renesas Renasas Single-Chip Microcomputer SH7086 Instrukcja Użytkownika Strona 13