Renesas Renasas Single-Chip Microcomputer SH7086 Instrukcja Użytkownika Pobierz pdf (Strona 63)

3.2 Functions

Chapter 3 Functions

AND

Logically AND

[ Related Instructions ] OR,XOR,TST

[ Function ]

AND AND

[ Syntax ]

AND.size (:format) src,dest

[ Selectable src/dest ]

[ Flag Change ]

Conditions

S : The flag is set when the operation resulted in MSB = 1; otherwise cleared.

Z : The flag is set when the operation resulted in 0; otherwise cleared.

[ Description Example ]

AND.B Ram:8[SB],R0L

AND.B:G A0,R0L

AND.B:G R0L,A0

AND.B:S #3,R0L

G , S (Can be specified)

B , W

[ Operation ]

dest src dest

src dest

R0L/R0 R0H/R1 R1L/R2 R1H/R3 R0L/R0 R0H/R1 R1L/R2 R1H/R3

A0/A0

A1/A1

[A0] [A1] A0/A0

A1/A1

[A0] [A1]

dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB] dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB]

dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16 dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 #IMM dsp:20[A0] dsp:20[A1] abs20 SP/SP

R2R0 R3R1 A1A0 R2R0 R3R1 A1A0

• This instruction logically ANDs

dest

and

src

together and stores the result in

dest

• If

dest

is an A0 or A1 when the size specifier (.size) you selected is (.B),

src

is zero-expanded to

perform calculation in 16 bits. If

src

is an A0 or A1, operation is performed on the eight low-order bits

of the A0 or A1.

; A0’s 8 low-order bits and R0L are ANDed.

; R0L is zero-expanded and ANDed with A0.

UIOBSZDC

(See the next page for

src

dest

classified by format.)

[ Instruction Code/Number of Cycles ]

Page=

149

Change

Flag

*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for

src

and

dest

simulta-

neously.

1 2 ... 58 59 60 61 62 63 64 65 66 67 68 ... 307 308

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