Renesas Asynchronous SH7145F Instrukcja Użytkownika Pobierz pdf (Strona 11)

SH7145 Group

SCI Break Detection

REJ06B0384-0100Z/Rev.1.00 September 2004 Page 11 of 20

5.2 SCI Routine

init_sci ()

return

Cancel the module standby states of

SCI0 and CMT0.

Set the period in CMCOR_0.

Initialize CMCNT_0.

Set the interrupt level of CMT0.

Clear the interrupt mask.

Set BRR_0 to set the communication speed

to 19200 bps.

Select LSB-first reception by the DIR bit

in SDCR_0.

Wait for 1-bit transfer period

or more.

Yes

Set CMCSR_0 to enable compare-match

interrupts and select Pφ/32 as the input

clock of CMCNT_0.

Clear the TIE, RIE, TE, RE, MPIE, and

TEIE bits in SCR_0 to 0.

Set SCR_0 to enable ERI interrupt.

Set PACRL2 to specify PA0 (pin130) to

function as RxD.

Set the RE bit in SCR_0 to 1 to enable

reception.

Select an internal clock as the clock source

by the CKE1 and CKE0 bits in SCR_0.

Set SMR_0 to select

asynchronous mode, 8-bit data length,

no parity, and 1 stop bit and set the clock

source for the baud-rate generator to Pφ.

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 19 20

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Renesas Asynchronous SH7145F Instrukcja Użytkownika Strona 11