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4. Reset Signals

The SH7211 reset signals are only valid during emulation started with clicking the GO or

STEP-type button. If these signals are enabled on the user system in command input wait state,

they are not sent to the SH7211.

Note: Do not break the user program when the _RES, _BREQ, or _WAIT signal is being low. A

TIMEOUT error will occur. If the _BREQ or _WAIT signal is fixed to low during break,

a TIMEOUT error will occur at memory access.

5. Direct Memory Access Controller (DMAC)

The DMAC operates even when the emulator is used. When a data transfer request is

generated, the DMAC executes DMA transfer.

6. Memory Access during User Program Execution

During execution of the user program, memory is accessed by the following two methods, as

shown in table 3.2.

Table 3.2 Memory Access during User Program Execution

Method Description

H-UDI read/write The stopping time of the user program is short because memory is

accessed by the dedicated bus master.

Short break The stopping time of the user program is long because the user program

temporarily breaks.

The method for accessing memory during execution of the user program is specified by using

the [Configuration] dialog box.

Table 3.3 Stopping Time by Memory Access (Reference)

Method Condition Stopping Time

H-UDI read/write Reading of one longword for the

internal RAM

Reading: Maximum three bus clock

cycles (Bφ)

Writing of one longword for the

internal RAM

Writing: Maximum two bus clock

cycles (Bφ)

Short break CPU clock: 40 MHz

JTAG clock: 1.25 MHz

Reading or writing of one byte, one

word, or one longword for the

external area

About 15 ms

1 2 ... 45 46 47 48 49 50 51 52 53 54 55 ... 89 90

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