
RENESAS TECHNICAL UPDATE TN-H8*-A407A/E Date:Mar.10.2009
Page 3 of 5
Section 13 I/O Ports
(1) Page 510, table 13.2
[Before Change]
Registers
Port
Number of
Pins
DDR DR PORT ICR PCR ODR
Ports 1 to
5
Description omitted (no changes)
Port 6 6 O O O O
Port A 8 O O O O
Port B 4 O O O O
Ports D*
1
to E*
1
Description omitted (no changes)
Port F 5 O O O O O O
Ports H to
K*
2
Description omitted (no changes)
Port M 5 O O O O
[Legend]
O: Register exists
: No register exists
Notes: 1. Do not access
port D or E registers when PCJKE 1.
2. Do not access port J or K registers when PCJKE 0.
[After Change]
Registers
Port
Number of
Pins
DDR DR PORT ICR PCR ODR
Ports 1 to
5
Description omitted (no changes)
Port 6*
3
6 O O O O
Port A 8 O O O O
Port B*
4
4 O O O O
Ports D*
1
to E*
1
Description omitted (no changes)
Port F*
5
5 O O O O O O
Ports H to
K*
2
Description omitted (no changes)
Port M*
6
5 O O O O
[Legend]
O: Register exists
: No register exists
Notes: 1. Do not access
port D or E registers when PCJKE 1.
2. Do not access port J or K registers when PCJKE 0.
3. For port 6, only the six lower-order bits are valid (the two higher-order bits are reserved). The write value should
always be the initial value.
4. For port B, only the four lower-order bits are valid (the four higher-order bits are reserved). The write value should
always be the initial value.
5. For port F, only the five lower-order bits are valid (the three higher-order bits are reserved). The write value should
always be the initial value.
6. For port M, only the five lower-order bits are valid (the three higher-order bits are reserved). The write value should
always be the initial value.
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