Renesas H8S/2138 Series Instrukcja Obsługi Pobierz pdf (Strona 128)

Microcomputer Technical Q&A

120

In both of the above cases, the TXI interrupt handling routine flowchart is as shown below.

TXI interrupt

count++

count = 16

Write (count)'th data byte to TDR

Clear TDRE (TDRE read-clear)

RTE

TIE = 0 (disable interrupts)

Yes

Applicable Products

Applicability Series Applicability Series Applicability Series

Yes Entire H8S Series H8S/2655 H8S/2350

H8S/2355 H8S/2357 H8S/2345

H8S/2245 H8S/2148 H8S/2144

H8S/2138 H8S/2134 H8S/2128

H8S/2124 — — — —

1 2 ... 123 124 125 126 127 128 129 130 131 132 133 ... 147 148

Application Note 1
Using this Application Note 4
Contents 5
Bus controller 6
Power-Down State 6
Electrical Characteristics 6
A/D Converter 8
I/O Ports 8
Clock Pulse Generator 8
Q&A No.: QAH8S-001 9
Q&A No.: QAH8S-002 10
Category: CPU 10
Q&A No.: QAH8S-003 12
Q&A No.: QAH8S-004 13
Q&A No.: QAH8S-005 14
Q&A No.: QAH8S-006 15
Subject: MAC Register 15
Q&A No.: QAH8S-007 16
Subject: EXR Register 16
Q&A No.: QAH8S-008 17
Category: Instruction 17
Subject: SUBX Instruction 17
Q&A No.: QAH8S-009 18
Subject: BRN Instruction 18
Q&A No.: QAH8S-010 19
Q&A No.: QAH8S-011 20
Q&A No.: QAH8S-012 21
Instruction 21
Q&A No.: QAH8S-013 22
Q&A No.: QAH8S-014 23
Subject: Stack Precautions 23
Q&A No.: QAH8S-015 24
Subject: Stack Pointer 24
Q&A No.: QAH8S-016 25
Subject: TAS Instruction 25
Q&A No.: QAH8S-017 26
Q&A No.: QAH8S-018 28
Q&A No.: QAH8S-019 30
Category: MCU Operating Modes 30
Subject: Mode Pins 30
Q&A No.: QAH8S-020 31
Subject: Use of RAME Bit 31
Q&A No.: QAH8S-021 32
Category: Exception Handling 32
Subject: Reset 32
Q&A No.: QAH8S-022 34
Category: Interrupts 34
Disabled 34
Q&A No.: QAH8S-023 35
Q&A No.: QAH8S-024 36
Q&A No.: QAH8S-025 37
Q&A No.: QAH8S-026 38
Q&A No.: QAH8S-027 39
Q&A No.: QAH8S-028 40
Q&A No.: QAH8S-029 41
Q&A No.: QAH8S-030 43
Q&A No.: QAH8S-031 44
Category: Bus Controller 44
Q&A No.: QAH8S-032 45
Subject: 45
Q&A No.: QAH8S-033 46
Subject: WAIT (1) 46
Q&A No.: QAH8S-034 47
Subject: WAIT (2) 47
Q&A No.: QAH8S-035 49
Q&A No.: QAH8S-036 51
Q&A No.: QAH8S-037 52
Q&A No.: QAH8S-038 53
Q&A No.: QAH8S-039 55
Q&A No.: QAH8S-040 56
Q&A No.: QAH8S-041 57
Q&A No.: QAH8S-042 58
Q&A No.: QAH8S-043 59
Q&A No.: QAH8S-044 60
Subject: 2-CAS DRAM Interface 60
Q&A No.: QAH8S-045 62
Category: Power-Down State 62
Subject: Medium-Speed Mode 62
Q&A No.: QAH8S-046 63
Q&A No.: QAH8S-047 64
Q&A No.: QAH8S-048 65
Q&A No.: QAH8S-049 66
Q&A No.: QAH8S-050 67
Subject: Module Stop Mode 67
Q&A No.: QAH8S-051 68
Q&A No.: QAH8S-052 69
Q&A No.: QAH8S-053 70
Subject: RD Signal Timing 70
Q&A No.: QAH8S-054 72
Category: Pins 72
Q&A No.: QAH8S-055 73
Q&A No.: QAH8S-056 74
Q&A No.: QAH8S-057 76
Q&A No.: QAH8S-058 77
Subject: WDTOVF Pin 77
Q&A No.: QAH8S-201 79
Category: DMAC 79
Q&A No.: QAH8S-202 80
Q&A No.: QAH8S-203 81
Q&A No.: QAH8S-204 82
Q&A No.: QAH8S-205 84
Function 84
Q&A No.: QAH8S-206 86
Q&A No.: QAH8S-207 87
Q&A No.: QAH8S-208 88
Q&A No.: QAH8S-209 90
Q&A No.: QAH8S-210 91
Q&A No.: QAH8S-211 92
Q&A No.: QAH8S-212 94
Subject: DREQ Signal Input 94
Q&A No.: QAH8S-213 95
Category: DTC 95
Subject: Nature of DTC 95
Q&A No.: QAH8S-214 96
Q&A No.: QAH8S-215 97
Q&A No.: QAH8S-216 98
Q&A No.: QAH8S-217 99
Q&A No.: QAH8S-218 100
Category: TPU 100
Q&A No.: QAH8S-219 101
Subject: Cascaded Connection 101
Q&A No.: QAH8S-220 102
Q&A No.: QAH8S-221 103
Q&A No.: QAH8S-222 104
Q&A No.: QAH8S-223 105
Subject: Two-Phase PWM Output 105
Applicable Products 106
Q&A No.: QAH8S-224 107
Category: WDT 107
Q&A No.: QAH8S-225 108
Category: SCI 108
Subject: SCI Initialization 108
Q&A No.: QAH8S-226 109
Q&A No.: QAH8S-227 110
Q&A No.: QAH8S-228 111
Q&A No.: QAH8S-229 112
Q&A No.: QAH8S-230 113
Q&A No.: QAH8S-231 114
Q&A No.: QAH8S-232 117
Q&A No.: QAH8S-233 118
Subject: RDRF Flag Set Timing 118
In Synchronous Mode 120
Q&A No.: QAH8S-234 121
Q&A No.: QAH8S-235 122
External Clock 122
Q&A No.: QAH8S-236 123
Q&A No.: QAH8S-237 124
Q&A No.: QAH8S-238 125
Q&A No.: QAH8S-239 126
Q&A No.: QAH8S-240 129
Subject: Data Transfer to TDR 129
Q&A No.: QAH8S-241 131
Subject: TDRE Flag Set Timing 131
2. Synchronous mode 134
Q&A No.: QAH8S-242 135
Q&A No.: QAH8S-243 136
Category: A/D Converter 136
Q&A No.: QAH8S-244 138
Q&A No.: QAH8S-245 140
Q&A No.: QAH8S-246 142
Category: I/O Ports 142
Q&A No.: QAH8S-247 143
Subject: Reserved Bits 143
Q&A No.: QAH8S-248 144
Subject: Disabling 144
Q&A No.: QAH8S-249 145
Q&A No.: QAH8S-250 146
Q&A No.: QAH8S-251 147

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