Renesas PCA4738F-80A Instrukcja Użytkownika Pobierz pdf (Strona 18)

17

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS

38C3 Group

b7 b0

Interrupt edge selection register

INT

0

interrupt edge selection bit

INT

1

interrupt edge selection bit

INT

2

interrupt edge selection bit

Not used (return “0” when read)

CNTR

0

active edge switch bit

CNTR

1

active edge switch bit

(INTEDGE : address 003A

16

)

Interrupt request register 1

INT

0

interrupt request bit

INT

1

interrupt request bit

INT

2

interrupt request bit

Serial I/O interrupt request bit

Timer A interrupt request bit

Timer 1 interrupt request bit

Timer 2 interrupt request bit

Timer 3 interrupt request bit

Interrupt control register 1

INT

0

interrupt enable bit

INT

1

interrupt enable bit

INT

2

interrupt enable bit

Serial I/O interrupt enable bit

Timer A interrupt enable bit

Timer 1 interrupt enable bit

Timer 2 interrupt enable bit

Timer 3 interrupt enable bit

0 : No interrupt request issued

1 : Interrupt request issued

(IREQ1 : address 003C

16

)

(ICON1 : address 003E

16

)

Interrupt request register 2

Timer 4 interrupt request bit

Timer 5 interrupt request bit

Timer 6 interrupt request bit

CNTR

0

interrupt request bit

CNTR

1

interrupt request bit

Key input interrupt request bit

AD conversion interrupt request bit

Not used (returns “0” when read)

(IREQ2 : address 003D

16

)

Interrupt control register 2

Timer 4 interrupt enable bit

Timer 5 interrupt enable bit

Timer 6 interrupt enable bit

CNTR

0

interrupt enable bit

CNTR

1

interrupt enable bit

Key input interrupt enable bit

AD conversion interrupt enable bit

Not used (returns “0” when read)

(Do not write “1” to this bit)

0 : Interrupts disabled

1 : Interrupts enabled

(ICON2 : address 003F

16

)

0 : Falling edge active

1 : Rising edge active

b7 b0

b7 b0

b7 b0

b7 b0

0 : Falling edge active, rising edge count

1 : Rising edge active, falling edge count

Interrupt request bit

Interrupt enable bit

Interrupt disable flag (I)

BRK instruction

Reset

Interrupt request

Fig. 13 Interrupt control

Fig. 14 Structure of interrupt-related registers

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 63 64

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