Renesas PROM Programming Adapter PCA7435FPG02 Instrukcja Użytkownika Strona 47

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Przeglądanie stron 46
7540 Group
Rev.4.00 Jun 21, 2004 page 47 of 82
REJ03B0011-0400Z
Fig. 53 State transition
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Oscillation stop detection circuit valid
CPUM412
MISRG112
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Interrupt
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WIT
instruction
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G102
CPUM312
CPUM302
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CPUM
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G112 M
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State 3
Operation clock source:
On-chip oscillator (Note 3)
f(X
IN
) oscillation enabled
On-chip oscillator enalbed
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Notes on switch of clock
(1) In operation clock source = f(X
IN
), the following can be
selected for the CPU clock division ratio.
f(X
IN
)/2 (high-speed mode)
f(X
IN
)/8 (middle-speed mode)
f(X
IN
) (double-speed mode, only at a ceramic oscillation)
(2) Execute the state transition state 3 to state 2 or
state 3’ to state 2’ after stabilizing X
IN
oscillation.
(3) In operation clock source = on-chip oscillator, the middle-
speed mode is selected for the CPU clock division ratio.
(4) When the state transition state 2 state 3 state 4
is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
• CPUM76 10
2
(State 2 state 3)
• NOP instruction
• CPUM4 1
2
(State 3 state 4)
Double-speed mode at on-chip oscillator: NOP 3
High-speed mode at on-chip oscillator: NOP 1
Middle-speed mode at on-chip oscillator: NOP 0
Reset state
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02
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State 3’
Operation clock source:
On-chip oscillator (Note 3)
f(X
IN
) oscillation enabled
On-chip oscillator enalbed
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