Renesas PROM Programming Adapter PCA7435FPG02 Instrukcja Użytkownika Pobierz pdf (Strona 34)

7540 Group

Rev.4.00 Jun 21, 2004 page 34 of 82

REJ03B0011-0400Z

Fig. 30 Block diagram of clock synchronous serial I/O1

Fig. 31 Operation of clock synchronous serial I/O1 function

Serial I/O

●Serial I/O1

Serial I/O1 can be used as either clock synchronous or asynchro-

nous (UART) serial I/O. A dedicated timer is also provided for

baud rate generation.

(1) Clock Synchronous Serial I/O Mode

Clock synchronous serial I/O1 mode can be selected by setting

the serial I/O1 mode selection bit of the serial I/O1 control register

(bit 6) to “1”.

For clock synchronous serial I/O1, the transmitter and the receiver

must use the same clock. If an internal clock is used, transfer is

started by a write signal to the TB/RB.

1/4

F/F

CLK1

Serial I/O1 status register

Serial I/O1 control register

RDY1

Receive buffer register

Address 0018

Receive shift register

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Clock control circuit

Shift clock

Serial I/O1 synchronous

clock selection bit

Frequency division ratio 1/(n+1)

Baud rate generator

Address 001C

BRG count source selection bit

Clock control circuit

Falling-edge detector

Transmit buffer register

Data bus

Address 0018

Shift clock

Transmit shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Transmit interrupt request (TI)

Transmit interrupt source selection bit

Address 0019

Data bus

Address 001A

Transmit shift register

RBF = 1

TSC = 1

TBE = 0

TBE = 1

TSC = 0

Transfer shift clock

(1/2 to 1/2048 of the internal

clock, or an external clock)

Serial output TxD

Serial input RxD

Write pulse to receive/transmit

buffer register (address 0018

)

Overrun error (OE)

detection

Notes

1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after

the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the

serial I/O1 control register.

2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial

data is output continuously from the TxD pin.

3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .

Receive enable signal

RDY1

1 2 ... 29 30 31 32 33 34 35 36 37 38 39 ... 87 88

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