Renesas MN4 Instrukcja Użytkownika Pobierz pdf (Strona 14)

V850E2/MN4 Timer Array Unit Control

R01AN0922EJ0100 Rev.1.00 Page 14 of 54

Jan 13, 2012

Figure 4.10 TAUAnTPS Register Format (4/4)

Setting example

TAUA1TPS = 0x000a; /* CK0:PCLK / 2^10 */

• TAUAn prescaler baudrate value register (TAUAnBRS)

This register specifies the division factor of prescaler clock CK3.

CK3 is generated by dividing CK3_PRE by the factor specified in this register plus one. The PCLK prescaler for

CK3_PRE is specified in TAUAnTPS.TAUAnPRS3[3:0].

This register does not use CK3. Setting this register is unnecessary.

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 56 57

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Renesas MN4 Instrukcja Użytkownika Strona 14