
8
P
PP
P40
40 40
40 t
tt
to
o o
o P
PP
P47
47 47
47 (
((
(p
pp
pi
ii
in
nn
ns
s s
s u
uu
us
ss
se
ee
ed
d d
d f
ff
fo
oo
or
r r
r AN
ANAN
AN0
0 0
0 t
tt
to
o o
o AN
ANAN
AN7 a
7 a7 a
7 and
nd nd
nd DA
DADA
DA0
0 0
0 t
tt
to
o o
o DA
DADA
DA1
11
1)
))
),
, ,
, AV
AVAV
AVcc
cccc
cc,
, ,
, AV
AVAV
AVss
ss ss
ss a
aa
and
nd nd
nd V
VV
Vre
rere
ref:
f:f:
f:
Figure 2.4 User System Interface Circuit for P40 to P47, AVcc, AVss and Vref Signals
IRQ0IRQ7 and WAIT:
The IRQ0 to IRQ7 and WAIT signals are input to the MCU and also
to the trace acquiring circuit. Therefore, the rising and falling time of these signals must be within
8 ns/v or shorter.
Figure 2.5 IRQ0IRQ7 and WAIT User System Interface Circuit
Komentarze do niniejszej Instrukcji