Renesas SuperH SH7710 E10A Informacje Techniczne Pobierz pdf (Strona 30)

Figure 2.3 [Window trace] Page

Notes: 1. When the [L-bus] or [I-bus] radio button is selected, the following bus cycles will be

traced.

•

L-bus: A bus cycle generated by the CPU is acquired. A bus cycle is also acquired

when the cache has been hit.

•

I-bus: A bus cycle generated by the CPU or DMA is acquired. A bus cycle is not

acquired when the cache has been hit. The address information acquired by the I-

bus is 28 bits and the upper 4 bits are displayed as ‘*’. The source cannot be

displayed in the [Trace] window.

When X/Y-RAM is accessed from the P0 space, the I-bus must be selected, and when

accessed from the P2 space, the L-bus must be selected. When a cache fill cycle is

acquired, I-bus must be selected.

2. Address setting when X/Y-bus is selected

To trace both the X/Y-bus when the X/Y-bus is accessed at the same time, the X-bus

condition must be set in channel A, and the Y-bus condition must be set in channel B.

1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 41 42

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Renesas SuperH SH7710 E10A Informacje Techniczne Strona 30