Renesas Single-Chip Microcomputer M34519T-MCU Dokumentacja Strona 38
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ASSP Lineup (CAN) (3/7)ASSP Lineup (CAN) (2/7)
Generic Name
V850E2/SG4-H (Under planning) V850E2/SJ4-H (Under planning) V850E2/SK4-H (Under development)
Part No.
µPD70F4013 µPD70F4014 µPD70F4015 µPD70F4016 µPD70F4017 µPD70F4018
CPU name
V850E2M V850E2M V850E2M
CPU performance (Dhrystone)
400 MIPS (@ 160 MHz) 400 MIPS (@ 160 MHz) 400 MIPS (@ 160 MHz)
Internal ROM
1 MB (ash) 1.5 MB (ash) 1 MB (ash) 1.5 MB (ash) 1.5 MB (ash) 2 MB (ash)
Internal RAM
96 KB 128 KB 96 KB 128 KB 128 KB 192 KB
Data ash
32 KB 32 KB 32 KB
External bus
interface
Bus type
Multiplexed SRAM I/F SDRAM I/F, multiplexed/separate SRAM I/F SDRAM I/F, multiplexed/separate SRAM I/F
Address bus
20 bits 24 bits 24 bits
Data bus
8/16 bits 8/16 bits 8/16/32 bits
Chip select signal
-
3 4
Memory controller
SRAM, etc. SDRAM, SRAM, etc. SDRAM, SRAM, etc.
Interrupt sources Internal
10 16 16
External
144 161 208
Timer/counter
32-bit timer: 4 ch
×
1 unit
16-bit timer: 16 ch
×
1 unit
32-bit timer: 4 ch
×
1 unit
16-bit timer: 16 ch
×
1 unit
32-bit timer: 4 ch
×
1 unit
16-bit timer: 16 ch
×
2 units
Watchdog timer
2 ch 2 ch 2 ch
Serial interface
UART/CSI
×
4 ch
CSI
×
2 ch
CSI (With FIFO)
×
2 ch
I
2
C
×
4 ch
CAN controller
×
1 ch
IEBus
×
1 ch
MediaLB
×
1 ch
UART/CSI
×
5 ch
CSI
×
2 ch
CSI (With FIFO)
×
3 ch
I
2
C
×
4 ch
CAN controller
×
2 ch
IEBus
×
1 ch
MediaLB
×
1 ch
UART/CSI
×
5 ch
CSI
×
2 ch
CSI (With FIFO)
×
3 ch
I
2
C
×
4 ch
CAN controller
×
2 ch
IEBus
×
1 ch
MediaLB
×
1 ch
A/D converter
10 bits
×
8 ch
×
1 unit 10 bits
×
16 ch
×
1 unit 10 bits
×
16 ch
×
1 unit
D/A converter
- - -
DMA controller
16 ch 16 ch 16 ch
Ports I/O
58 100 127
Input
- - -
Debug control unit
Provided (RUN/break) Provided (RUN/break) Provided (RUN/break)
Ethernet controller
- -
1 ch
Other peripheral functions
Power-on clear (option), LVI, clock monitor, data CRC,
Hardware bus common memory: 32 KB, SSCG
Power-on clear (option), LVI, clock monitor, data CRC,
Hardware bus common memory: 32 KB, SSCG
Power-on clear (option), LVI, clock monitor, data CRC,
Hardware bus common memory: 32 KB, SSCG
Operating frequency
When using main clock: 160 MHz (max.)
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
When using main clock: 160 MHz (max.)
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
When using main clock: 160 MHz (max.)
When using subclock: 32.768 kHz
When using high-speed internal oscillation clock: 8 MHz
When using low-speed internal oscillation clock: 240 kHz
Power supply voltage
1.1 V to 1.3 V (internal)/3.0 V to 3.6 V (external) 1.1 V to 1.3 V (internal)/3.0 V to 3.6 V (external) 1.1 V to 1.3 V (internal)/3.0 V to 3.6 V (external)
Package
100-pin LQFP (14
×
14 mm) 144-pin LQFP (20
×
20 mm) 176-pin LQFP (24
×
24 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
105
°
C
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
105
°
C
-
40
°
C to
+
85
°
C,
-
40
°
C to
+
105
°
C
Numbers of channels indicate the total number implemented on the product. The actual number of usable channels differs depending on multi-use pin settings.
Generic Name
V850ES/JE3-E (Under development) V850ES/JF3-E (Under development) V850ES/JG3-E (Under development)
Part No.
µPD70F3829 µPD70F3833 µPD70F3837
CPU name
V850ES V850ES V850ES
CPU performance (Dhrystone)
103 MIPS (@ 50 MHz) 103 MIPS (@ 50 MHz) 103 MIPS (@ 50 MHz)
Internal ROM
256 KB (ash) 256 KB (ash) 256 KB (ash)
Internal RAM
64 KB (Including 16 KB of data-only RAM) 64 KB (Including 16 KB of data-only RAM) 64 KB (Including 16 KB of data-only RAM)
External bus
interface
Bus type
- - -
Address bus
- - -
Data bus
- - -
Chip select signal
- - -
Memory controller
- - -
Interrupt sources Internal
66 (Including one NMI) 67 (Including one NMI) 70 (Including one NMI)
External
11 (11)* (Including one NMI) 20 (20)* (Including one NMI) 22 (22)* (Including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
4 ch
16-bit timer/event counter (TAB)
×
1 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
16-bit timer/event counter (TAA)
×
4 ch
16-bit timer/event counter (TAB)
×
1 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
16-bit timer/event counter (TAA)
×
4 ch
16-bit timer/event counter (TAB)
×
1 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
Watchdog timer
1 ch 1 ch 1 ch
Serial interface
UART (LIN compatible)/CSI
×
1 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
CSI
×
1 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
UART (LIN compatible)/CSI
×
1 ch
UART (LIN compatible)/CSI/I
2
C
×
2 ch
CSI
×
2 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
UART (LIN compatible)/CSI
×
1 ch
UART (LIN compatible)/CSI/I
2
C
×
2 ch
CSI
×
2 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
A/D converter
10 bits
×
8 ch 10 bits
×
8 ch 10 bits
×
10 ch
D/A converter
- - -
DMA controller
4 ch 4 ch 4 ch
Ports I/O
29 41 64
Input
- - -
Debug control unit
Provided (RUN/break) Provided (RUN/break) Provided (RUN/break)
USB controller
USB 2.0 function (full-speed)
×
1 ch USB 2.0 function (full-speed)
×
1 ch USB 2.0 function (full-speed)
×
1 ch
Ethernet controller
1 ch 1 ch 1 ch
Other peripheral functions
Real-time counter (RTC), LVI/clock monitor, CRC, RAM retention ag Motor control, real-time counter (RTC), LVI/clock monitor,
CRC, RAM retention ag
Motor control, real-time counter (RTC), real-time output,
LVI/clock monitor, CRC, RAM retention ag
Operating frequency
When using main clock: 24 to 50 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
When using main clock: 24 to 50 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
When using main clock: 24 to 50 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V) 2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V) 2.85 V to 3.6 V (A /D converter, USB controller: 3.0 V to 3.6 V)
Package
64-pin LQFP (10
×
10 mm), 64-pin WQFN (9
×
9 mm) 80-pin LQFP (12
×
12 mm) 100-pin LQFP (14
×
14 mm), 121-pin FBGA (8
×
8 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
Generic Name
V850ES/JH3-E V850ES/JJ3-E
Part No.
µPD70F3783 µPD70F3786
CPU name
V850ES V850ES
CPU performance (Dhrystone)
103 MIPS (@ 50 MHz) 103 MIPS (@ 50 MHz)
Internal ROM
512 KB (ash) 512 KB (ash)
Internal RAM
124 KB (including 64 KB of data-only RAM) 124 KB (including 64 KB of data-only RAM)
External bus
interface
Bus type
Multiplexed/separate Multiplexed/separate
Address bus
22 bits 24 bits
Data bus
8/16 bits 8/16 bits
Chip select signal
3 2
Memory controller
SRAM, etc. SRAM, etc.
Interrupt sources Internal
82 (Including one NMI) 88 (Including one NMI)
External
22 (22)*
1
(Including one NMI) 27 (27)*
1
(Including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
6 ch
16-bit timer/event counter (TAB)
×
2 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
16-bit timer/event counter (TAA)
×
6 ch
16-bit timer/event counter (TAB)
×
2 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
Watchdog timer
1 ch 1 ch
Serial interface
UART (LIN compatible)/CSI
×
1 ch
UART (LIN compatible)/CSI (with FIFO)
×
1 ch
UART (with FIFO)/CSI
×
2 ch*
2
UART (LIN compatible)/CSI/I
2
C
×
2 ch
UART (LIN compatible)/CSI (with FIFO)*
3
/I
2
C
×
1 ch
CSI (with FIFO)*
3
×
1 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
UART (LIN compatible)/CSI
×
3 ch
UART (LIN compatible)/CSI (with FIFO)
×
1 ch
UART (with FIFO)/CSI
×
2 ch*
2
UART (LIN compatible)/CSI/I
2
C
×
2 ch
UART (LIN compatible)/CSI (with FIFO)*
3
/I
2
C
×
1 ch
CSI (with FIFO)*
3
×
1 ch
I
2
C
×
1 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
A/D converter
10 bits
×
10 ch 10 bits
×
12 ch
D/A converter
- -
DMA controller
4 ch 4 ch
Ports I/O
84 100
Input
- -
Debug control unit
Provided (RUN/break) Provided (RUN/break)
USB controller
USB 2.0 function (full-speed)
×
1 ch USB 2.0 function (full-speed)
×
1 ch
Ethernet controller
1 ch 1 ch
Other peripheral functions
Motor control, real-time counter (RTC), real-time output, LVI/clock monitor, CRC, RAM retention ag Motor control, real-time counter (RTC), real-time output, LVI/clock monitor, CRC, RAM retention ag
Operating frequency
When using main clock: 24 to 50 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
When using main clock: 24 to 50 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage
2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V) 2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V)
Package
128-pin LQFP (14
×
20 mm) 144-pin LQFP (20
×
20 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
*1. The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
*2. One channel is assigned to two different pins.
*3. The same channel is assigned to two different pins.
Generic Name
V850ES/JC3-H V850ES/JE3-H
Part No.
µPD70F3819 µPD70F3825
CPU name V850ES V850ES
CPU performance (Dhrystone) 98 MIPS (@ 48 MHz) 98 MIPS (@ 48 MHz)
Internal ROM 256 KB (ash) 256 KB (ash)
Internal RAM 24 KB 24 KB
External bus
interface
Bus type
- -
Address bus
- -
Data bus
- -
Chip select signal
- -
Memory controller
- -
Interrupt sources Internal 58 (Including one NMI) 58 (Including one NMI)
External 10 (10)* (Including one NMI) 11 (11)* (Including one NMI)
Timer/counter
16-bit timer/event counter (TAA)
×
4 ch
16-bit timer/event counter (TAB)
×
1 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
16-bit timer/event counter (TAA)
×
4 ch
16-bit timer/event counter (TAB)
×
1 ch
16-bit timer/event counter (TMT)
×
1 ch
16-bit interval timer (TMM)
×
4 ch
Watchdog timer 1 ch 1 ch
Serial interface UART (LIN compatible)/CSI
×
2 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
CSI
×
1 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
UART (LIN compatible)/CSI
×
2 ch
UART (LIN compatible)/CSI/I
2
C
×
1 ch
CSI
×
1 ch
UART (LIN compatible)/I
2
C/CAN
×
1 ch
A/D converter 10 bits
×
6 ch 10 bits
×
10 ch
D/A converter 8 bits
×
1 ch 8 bits
×
1 ch
DMA controller 4 ch 4 ch
Ports I/O 32 45
Input
- -
Debug control unit Provided (RUN/break) Provided (RUN/break)
USB controller USB 2.0 function (full-speed)
×
1 ch USB 2.0 function (full-speed)
×
1 ch
Other peripheral functions Real-time counter (RTC), real-time output, LVI/clock monitor, CRC, RAM retention ag Motor control, real-time counter (RTC), real-time output, LVI/clock monitor, CRC, RAM retention ag
Operating frequency
When using main clock: 24 to 48 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
When using main clock: 24 to 48 MHz
When using subclock: 32.768 kHz
When using internal oscillation clock: 220 kHz
Power supply voltage 2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V) 2.85 V to 3.6 V (A/D converter, USB controller: 3.0 V to 3.6 V)
Package 48-pin LQFP (7
×
7 mm), 48-pin WQFN (7
×
7 mm) 64-pin LQFP (10
×
10 mm), 64-pin WQFN (9
×
9 mm)
Operating ambient temperature
-
40
°
C to
+
85
°
C
-
40
°
C to
+
85
°
C
* The gure in parentheses indicates the number of external interrupts that can be used to release STOP mode.
74 75
- 32-bit Microcontrollers 1
- Roadmap/Features 3
- Development environment 4
- Product Lineup 10
- CPU Roadmap 13
- CPU Comparison 13
- PFESiP Roadmap 13
- V850 Architecture 14
- Object Code Size Comparison 15
- (Dhrystone 1.1/Large model) 15
- V850E2, V850E2M Architecture 16
- V850E1, V850ES Architecture 16
- Memory Access 17
- Analog Circuits 17
- Timer/Counter 18
- Serial Interface 18
- Selector 19
- Detection level selection 19
- ResistorResistorResistor 19
- Ubiquitous Corporation 20
- V850 Benchmark 21
- Low Power Consumption 21
- Solutions for V850 22
- Features 23
- Rewrite Modes 23
- Flash Specification List 23
- 5 V Operation 3 V Operation 24
- 3 V Operation 3 V Operation 25
- V850E/MA3 V850E2/ME3 29
- V850E/ME2 29
- V850E/IG4 V850E/IH4 30
- V850E/IG4-H V850E/IH4-H 30
- V850E/IG3 V850E/IF3 30
- V850E/MA3 30
- V850E/IA1 V850E/IA2 31
- V850E/IA4 V850E/IA3 31
- V850ES/HG3 V850ES/HJ3 31
- V850ES/HE3 V850ES/HF3 31
- V850ES/IK1 V850ES/IE2 32
- V850E/DJ3 V850E/DL3 32
- V850E/DG3 V850E/DJ3 32
- V850ES/FJ3 V850ES/FK3 35
- V850ES/FE3-L 36
- V850ES/FF3-L V850ES/FG3-L 36
- V850ES/FE2 V850ES/FF2 36
- V850ES/FG2 V850ES/FJ2 36
- ASSP Lineup (CAN) (1/7) 37
- V850ES/JH3-E V850ES/JJ3-E 38
- V850ES/JC3-H V850ES/JE3-H 38
- V850ES/SG3 39
- V850ES/SJ3 39
- V850E/SJ3-H 39
- V850E/SJ3-H V850E/SK3-H 40
- V850ES/SG2-H V850ES/SG2 40
- V850ES/SJ2-H V850ES/SJ2 40
- V850ES/SG1 41
- V850 Development Environment 43
- Installation 44
- Building 44
- Debugging 44
- Emulator 45
- Flash Memory Programmers 46
- Production 47
- Development Tools 48
- Microcontrollers Website 49
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