Renesas H8S/2378F Informacje Techniczne Pobierz pdf (Strona 94)

7.2 Main Processing and ROM Main Processing

7.2.1 Module Hierarchical Structure

The module hierarchical structure of main processing and ROM main processing is shown in Figure 7-1.

RESET_VECTOR (0x0000) Reset vector

⏐⎯startup (0x1000) Start

⏐⎯main Main processing

⏐⎯InitSCI SCI initial setting

⏐⎯RomMain ROM main processing

⏐⎯TransStart Transfer start

⏐⎯CmdFunc Command function

⏐⎯RamMain (0xFF4000) RAM main processing

Figure 7-1 Module Hierarchical Structure of Main Processing and ROM Main Processing

The reset vector causes a branch to start, which sets the stack pointer (Strt2378.src) and branches to main processing

(main in GenTest.c).

Main processing performs initial setting for the SCI (InitSCI in GenTest.c) to enable transmission/reception and causes

a branch to ROM main processing (RomMain in Ugenu.c).

ROM main processing transfers RAM main processing and others to RAM (TransStart in Ugenu.c) and processes

commands (CmdFunc in Ugenu.c). At the end of data, ROM main processing branches to RAM main processing

(RamMain in FDTUMain.c).

Main processing and ROM main processing are executed in ROM.

7.2.2 Reset Vectors (GenTest.c and GenTest.h)

The reset vectors are shown below:

(1) GenTest.c

/*Declare the vector table*/

#pragma section _VECT

const DWORD RESET_VECTOR = (DWORD)RESET_JMP_ADDRESS;

#pragma section

(2) GenTest.h

#define RESET_JMP_ADDRESS 0x1000

1 2 ... 89 90 91 92 93 94 95 96 97 98 99 ... 108 109

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Renesas H8S/2378F Informacje Techniczne Strona 94