Renesas CPU Board M3A-HS19 Informacje Techniczne Pobierz pdf (Strona 24)

Features and Specifications

2.3.3 External Synchronous DRAM

Rev.1.01

Oct 28, .2008 2-8

REJ10J1351-0101

Figure 2.3.4 shows a timing example of SDRAM mode register writing.

Tpw Trr

CKIO

Trc Trc

Tnop

Tmw

PALL

DESL

REF

DESL DESL

Hi-Z

(High)

CS3#

RASL#

CASL#

RD/WR#

DQMUU-LL

D15-0

A11-A1(A9-A0)

A12(A10/AP)

SDRAM

Command

[Symbols Descriptions]

PALL

: All bank precharge command

REF : Auto-refreshing command

MRS

: Mode register write commamd

DESL

: Deselect command

REF

DESL

MRS

DESL

DESL REF

DESL

Trc Trc

Trc

TrcTrr

Trr

REF command is issued 8 times

tRCtRP

Figure 2.3.4 Timing Example of SDRAM Mode Register Writing

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 ... 73 74

To our customers 1
Table of Contents 5
Overview 7
Chapter1 7
1.1 Overview 8
1.2 Configuration 8
1.3 External Specifications 9
Overview 10
1.4 Appearance 10
SH7619 CPU Board 11
M3A-HS19 11
1.6 M3A-HS19 Board Overview 12
1.7 M3A-HS19 Memory Mapping 14
Chapter2 17
Features and Specifications 17
2.1 Features 18
2.2 CPU 19
2.3 Memory 20
2.4 Serial Port Interface 29
2.5 PCMCIA Card Interface 30
SH7619 (U1) 31
RJ-45 (J5) 31
2.7 I/O Port 32
2.8 Power Supply Circuit 35
2.9 Clock Module 36
2.10 Reset Module 37
2.11 Interrupt Switch 38
2.12 E10A-USB Interface 39
Chapter3 41
Operational Specifications 41
3.1 M3A-HS19 Connectors 42
Board Edge 43
Top view of 46
3.2 Switches and LEDs 55
3.3 Dimensions 60
Appendix 61
M3A-HS19 SCHEMATICS 61
DK30575-C 63
User’s Manual 74

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