REJ05B0601-0102/Rev.1.02 April 2005 Page 2 of 13
M16C/80, M32C/84 Group
Differences between M16C/80 and M32C/84
Table 3.1.2 Function Differences (2) (Note1)
Note 1: About the details and the characteristics, refer to hardware manual.
Note 2: I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
Note 3: IEBus is a trademark of NEC Electronics Corporation.
Item M16C/80 M32C/84
DMA Request Factors Falling edge or both edges of input signals to
the INT0
________
to INT3
________
pin
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 to UART4 transmit and receive
interrupt requests
A/D conversion interrupt request
Software trigger
The next interrupt is added to M16C/80.
Intelligent I/O interrupt request
CAN interrupt request
DMACII Function None Have
Timer A, Timer B
Count Source
Selectable: f1, f8, f32, fC32
Selectable: f1, f8, f2n, fC32 (n=0 to 15,.No division
when n=0)
Three-Phase Motor Control
Timer
Dead Time
Have Selectable
Three-Phase Motor Control
Timer
Dead Time Trigger
Fixed Selectable
Three-Phase Motor Control
Timer
Count Source
Selectable: f1, f8, f32
, fC32 Selectable: f1, f8, f2n, fC32 (n=0 to 15. No division
when n=0)
Serial I/O (Clock synchronous serial I/O, Clock
asynchronous serial I/O) × 2
(Clock synchronous serial I/O, Clock
asynchronous serial I/O , I
2
C bus
TM
(Note 2),
IEBus
TM
(Note 3), SIM interface) × 3
(Clock synchronous serial I/O, Clock asynchronous
serial I/O, I
2
C bus
TM
(Note 2), IEBus
TM
(Note 3), GCI
bus, SIM interface) × 5
Serial I/O
CTS
________
/RTS
_______
Separate
Function
Can be used in UART0 None
Serial I/O
Transfer Clock Output
from Multiple Pins
Can be used in UART1 None
Serial I/O
TxD, RxD I/O Polarity
Switching Function
Can be used in UART2 to UART4 Can be used in UART0 to UART4
Serial I/O
Sleep Function
Can be used in UART0, UART1 None
Serial I/O
Count Source
Selectable: f1, f8, f32
f1, f8, f2n(n=0 to 15. No division when n=0)
Serial I/O
Overrun error occur timing
This error occurs when the next data is ready
before contents of UiRB register (i=0 to 4) are
read out
This error occurs if the serial I/O started receiving the
next data before reading the UiRB register (i=0 to 4)
and received the 7th bit of the next data (Clock
synchronous serial I/O).
This error occurs if the serial I/O started receiving the
next data before reading the UiRB register and
received the bit one before the last stop bit of the next
data (Clock asynchronous serial I/O).
Serial I/O
UART Mode
RTS
_______
Timing
Assert low when reception is completed Assert low when receive buffer is read
Serial I/O
I
2
C Mode
Start condition, stop condition:
Not auto-generation
Start condition, stop condition: Auto-generation
Serial I/O
I
2
C mode
SDA delay
SDA digital delay count source: 1/f(XIN) SDA digital delay count source: BRG
CAN Module None 1 channel
Intelligent I/O None 1 group
A/D Converter 1 circuit, 10 channels 1 circuits, 34 channels (26 channel: 100-pin version)
(33 strony)
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