Renesas H8S/2111B Instrukcja Użytkownika Pobierz pdf (Strona 315)

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Rev. 1.00, 05/04, page 281 of 544

13.3 Register Descriptions

The I

C bus interface has the following registers. Registers ICDR and SARX and registers ICMR

and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit

in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit

is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, see

section 3.2.3, Serial Timer Control Register (STCR).

• I

C bus data register (ICDR)

• Slave address register (SAR)

• Second slave address register (SARX)

• I

C bus mode register (ICMR)

• I

C bus control register (ICCR)

• I

C bus status register (ICSR)

• DDC switch register (DDCSWR)*

• I

C bus extended control register (ICXR)

• Port G control register (PGCTL)*

Notes: 1. DDCSWR is available only for IIC_0.

2. PGCTL register is common to IIC_0 and IIC_1.

1 2 ... 310 311 312 313 314 315 316 317 318 319 320 ... 581 582

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