Renesas H8S/2111B Instrukcja Użytkownika

Revision Date: May. 14, 200416 H8S/2111BHardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series H8S/2111B H

Rev. 1.00, 05/04, page x of xxxiv 2.8 Processing States...

Rev. 1.00, 05/04, page 66 of 544

Rev. 1.00, 05/04, page 67 of 544 Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can

Rev. 1.00, 05/04, page 68 of 544 SYSCRNMI inputIRQ inputInternal interrupt request WOVI0 to IBFI3NMIEGINTM1, INTM0NMI inputIRQ inputISRISCRIERICRInte

Rev. 1.00, 05/04, page 69 of 544 5.3 Register Descriptions The interrupt controller has the following registers. For details on the system control re

Rev. 1.00, 05/04, page 70 of 544 Table 5.2 Correspondence between Interrupt Source and ICR Register Bit Bit Name ICRA ICRB ICRC 7 ICRn7 IRQ0 — —

Rev. 1.00, 05/04, page 71 of 544 5.3.3 Break Address Registers A to C (BARA to BARC) The BAR registers specify an address that is to be a break addre

Rev. 1.00, 05/04, page 72 of 544 5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt r

Rev. 1.00, 05/04, page 73 of 544 5.3.5 IRQ Enable Register (IER) IER controls the enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit Bit

Rev. 1.00, 05/04, page 74 of 544 • KMIMRA Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR1

Rev. 1.00, 05/04, page 75 of 544 Figure 5.2 shows the relationship between interrupts IRQ7 and IRQ6, interrupts KIN15 to KIN0, interrupts WUE7 to WUE

Rev. 1.00, 05/04, page xi of xxxiv 5.4.1 External Interrupts ...

Rev. 1.00, 05/04, page 76 of 544 5.4 Interrupt Sources 5.4.1 External Interrupts There are four types of external interrupts: NMI, IRQ7 to IRQ0, KIN1

Rev. 1.00, 05/04, page 77 of 544 When pin IRQ7 is used as an IRQ7 interrupt pin, set all of bits KMIMR15 to KMIMR8 and WUEMR7 to WUEMR0 to 1. If any

Rev. 1.00, 05/04, page 78 of 544 5.5 Interrupt Exception Handling Vector Table Table 5.3 lists interrupt exception handling sources, vector addresse

Rev. 1.00, 05/04, page 79 of 544 Vector Address Origin of Interrupt Source Name Vector NumberNormal Mode Advanced Mode ICR Priority TMR_0 CMIA0 (Comp

Rev. 1.00, 05/04, page 80 of 544 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: Interrupt control mode

Rev. 1.00, 05/04, page 81 of 544 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling rou

Rev. 1.00, 05/04, page 82 of 544 5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for IRQ and on-

Rev. 1.00, 05/04, page 83 of 544 Figure 5.6 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corre

Rev. 1.00, 05/04, page 84 of 544 Program excution stateInterrupt generated?NMIAn interrupt with interrupt control level 1?IRQ0IRQ1IFBFI3IRQ0IRQ1IFBFI

Rev. 1.00, 05/04, page 85 of 544 5.6.3 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example

Rev. 1.00, 05/04, page xii of xxxiv 7.4 Port 4...

Rev. 1.00, 05/04, page 86 of 544 5.6.4 Interrupt Response Times Table 5.5 shows interrupt response times − the intervals between generation of an int

Rev. 1.00, 05/04, page 87 of 544 5.7 Address Break 5.7.1 Features This LSI can determine the specific address prefetch by the CPU to generate an addr

Rev. 1.00, 05/04, page 88 of 544 5.7.3 Operation If the CPU prefetches an address specified in BAR by setting ABRKCR and BAR, an address break interr

Rev. 1.00, 05/04, page 89 of 544 Figure 5.9 shows an example of address timing. InstructionfetchAddress busBreak request signalBreak pointNOP instruc

Rev. 1.00, 05/04, page 90 of 544 5.8 Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to

Rev. 1.00, 05/04, page 91 of 544 5.8.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. Af

Rev. 1.00, 05/04, page 92 of 544

Rev. 1.00, 05/04, page 93 of 544 Section 6 Bus Controller (BSC) Since this LSI does not have an externally extended function, it does not have an o

Rev. 1.00, 05/04, page 94 of 544 6.1.2 Wait State Control Register (WSCR) Bit Bit Name Initial Value R/W Description 7 6 — — 0 0 R/W R/W Reserved T

Rev. 1.00, 05/04, page 95 of 544 Section 7 I/O Ports This LSI has fifteen I/O ports (ports 1 to 6, 8, 9, and A to G), and one input-only port (port

Rev. 1.00, 05/04, page xiii of xxxiv 7.12.5 Pin Functions ...

Rev. 1.00, 05/04, page 96 of 544 Table 7.1 Port Functions Port Description Mode 2and Mode 3 I/O Status Port 1 General I/O port also functioning

Rev. 1.00, 05/04, page 97 of 544 Port Description Mode 2and Mode 3 I/O Status Port 6 General I/O port also functioning as interrupt input, FRT in

Rev. 1.00, 05/04, page 98 of 544 Port Description Mode 2and Mode 3 I/O Status Port A General I/O port also functioning as key-sense interrupt inp

Rev. 1.00, 05/04, page 99 of 544 Port Description Mode 2and Mode 3 I/O Status Port E General I/O port PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 On-chip in

Rev. 1.00, 05/04, page 100 of 544 7.1 Port 1 Port 1 is an 8-bit I/O port. Port 1 pins also function as PWM output pins. Port 1 has the following regi

Rev. 1.00, 05/04, page 101 of 544 7.1.3 Port 1 Pull-Up MOS Control Register (P1PCR) P1PCR controls the on/off state of the port 1 on-chip input pull

Rev. 1.00, 05/04, page 102 of 544 7.1.5 Port 1 Input Pull-Up MOS Port 1 has an on-chip input pull-up MOS function that can be controlled by software

Rev. 1.00, 05/04, page 103 of 544 7.2.2 Port 2 Data Register (P2DR)) P2DR stores output data for port 2. Bit Bit Name Initial Value R/W Description

Rev. 1.00, 05/04, page 104 of 544 7.2.5 Port 2 Input Pull-Up MOS Port 2 has an on-chip input pull-up MOS function that can be controlled by software

Rev. 1.00, 05/04, page 105 of 544 7.3.2 Port 3 Data Register (P3DR) P3DR stores output data of port 3. Bit Bit Name Initial Value R/W Description 7

Rev. 1.00, 05/04, page xiv of xxxiv 9.3.7 Timer Control/Status Register (TCSR)... 163 9

Rev. 1.00, 05/04, page 106 of 544 7.3.4 Pin Functions • P37/SERIRQ, P36/LCLK, P35/LRESET, P34/LFRAME, P33/LAD3, P32/LAD2, P31/LAD1, P30/LAD0 The pin

Rev. 1.00, 05/04, page 107 of 544 7.4 Port 4 Port 4 is an 8-bit I/O port. Port 4 pins also function as TMR_0 and TMR_1 I/O pins, and the IIC_1 I/O pi

Rev. 1.00, 05/04, page 108 of 544 7.4.3 Pin Functions • P47 The pin function is switched as shown below according to the combination of the P47DDR b

Rev. 1.00, 05/04, page 109 of 544 • P43/TMCI1 The pin function is switched as shown below according to the state of the P43DDR bit. P43DDR 0 1 P43

Rev. 1.00, 05/04, page 110 of 544 7.5 Port 5 Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI_1 extended I/O pins, and the IIC_0 I/O pin.

Rev. 1.00, 05/04, page 111 of 544 7.5.3 Pin Functions • P52/ExSCK1*/SCL0 The pin function is switched as shown below according to the combination of

Rev. 1.00, 05/04, page 112 of 544 • P50/ExTxD1 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_

Rev. 1.00, 05/04, page 113 of 544 7.6.2 Port 6 Data Register (P6DR) P6DR stores output data for port 6. Bit Bit Name Initial Value R/W Description

Rev. 1.00, 05/04, page 114 of 544 7.6.4 System Control Register 2 (SYSCR2) SYSCR2 is not available in this LSI although originally designed to contr

Rev. 1.00, 05/04, page 115 of 544 • P66/FTOB/KIN6/IRQ6 The pin function is switched as shown below according to the combination of the OEB bit in TO

Rev. 1.00, 05/04, page xv of xxxiv 10.5.1 TCNT Count Timing ...

Rev. 1.00, 05/04, page 116 of 544 • P61/FTOA/KIN1 The pin function is switched as shown below according to the combination of the OEA bit in TOCR of

Rev. 1.00, 05/04, page 117 of 544 7.7 Port 7 Port 7 is an 8-bit input only port. Port 7 pins also function as the A/D converter analog input pins. Po

Rev. 1.00, 05/04, page 118 of 544 7.8 Port 8 Port 8 is an 8-bit I/O port. Port 8 pins also function as SCI_1 I/O pins, the IIC_1 I/O pins, LPC I/O pi

Rev. 1.00, 05/04, page 119 of 544 7.8.3 Pin Functions • P86/IRQ5/SCK1/SCL1 The pin function is switched as shown below according to the combination

Rev. 1.00, 05/04, page 120 of 544 • P84/IRQ3/TxD1 The pin function is switched as shown below according to the combination of the TE bit in SCR of S

Rev. 1.00, 05/04, page 121 of 544 • P81/GA20 The pin function is switched as shown below according to the combination of the FGA20E bit in HICR0 and

Rev. 1.00, 05/04, page 122 of 544 7.9 Port 9 Port 9 is an 8-bit I/O port. Port 9 pins also function as the interrupt input pins, IIC_0 I/O pin, subcl

Rev. 1.00, 05/04, page 123 of 544 7.9.3 Pin Functions • P97/SDA0 The pin function is switched as shown below according to the combination of the ICE

Rev. 1.00, 05/04, page 124 of 544 • P92/IRQ0 The pin function is switched as shown below according to the state of the P92DDR bit. P92DDR 0 1 P92

Rev. 1.00, 05/04, page 125 of 544 7.10 Port A Port A is an 8-bit I/O port. Port A pins also function as keyboard buffer controller I/O pins, and key-

Rev. 1.00, 05/04, page xvi of xxxiv 11.6.5 System Reset by RESO Signal ...

Rev. 1.00, 05/04, page 126 of 544 7.10.3 Port A Input Data Register (PAPIN) PAPIN indicates the port A state. Bit Bit Name Initial Value R/W Des

Rev. 1.00, 05/04, page 127 of 544 • PA5/KIN13/PS2BD The pin function is switched as shown below according to the combination of the KBIOE bit in KBC

Rev. 1.00, 05/04, page 128 of 544 • PA2/KIN10/PS2AC The pin function is switched as shown below according to the combination of the KBIOE bit in KBC

Rev. 1.00, 05/04, page 129 of 544 7.11 Port B Port B is an 8-bit I/O port. Port B pins also have LPC input/output pins, and wakeup event interrupt in

Rev. 1.00, 05/04, page 130 of 544 7.11.3 Port B Input Data Register (PBPIN) PBPIN indicates the port B state. Bit Bit NameInitial Value R/W Descript

Rev. 1.00, 05/04, page 131 of 544 • PB0/WUE0/LSMI The pin function is switched as shown below according to the combination of the LSMIE bit in HICR

Rev. 1.00, 05/04, page 132 of 544 7.12 Ports C, D Port C and port D are two sets of 8-bit I/O ports. Port C and port D have the following registers.

Rev. 1.00, 05/04, page 133 of 544 7.12.2 Port C and Port D Output Data Registers (PCODR, PDODR) PCODR and PDODR store output data for the pins on po

Rev. 1.00, 05/04, page 134 of 544 Bit Bit NameInitial Value R/W Description 7 PD7PIN Undefined* R 6 PD6PIN Undefined* R 5 PD5PIN Undefined* R 4 PD4PI

Rev. 1.00, 05/04, page 135 of 544 7.12.5 Pin Functions DDR 0 1 NOCR — 0 1 ODR 0 1 0 1 0 1 N-ch. driver OFF ON OFF ON OFF P-ch. driver OFF OFF

Rev. 1.00, 05/04, page xvii of xxxiv 12.8.6 SCI Operations during Mode Transitions ... 273

Rev. 1.00, 05/04, page 136 of 544 7.13 Ports E, F Ports E and F are two sets of 8-bit I/O ports. Port F also functions as I/O pins for TMR_X*, TMR_Y

Rev. 1.00, 05/04, page 137 of 544 7.13.2 Port E and Port F Output Data Registers (PEODR, PFODR) PEODR and PFODR store output data for the pins on po

Rev. 1.00, 05/04, page 138 of 544 7.13.3 Port E and Port F Input Data Registers (PEPIN, PFPIN) Reading PEPIN and PFPIN always returns the pin states

Rev. 1.00, 05/04, page 139 of 544 • PF6/ExTMOX The pin function is switched as shown below according to the combination of the IOSX bit* in TCRXY of

Rev. 1.00, 05/04, page 140 of 544 • PF2/TMOA The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR

Rev. 1.00, 05/04, page 141 of 544 Bit Bit Name Initial Value R/W Description 7 PF7NOCR 0 R/W 6 PF6NOCR 0 R/W 5 PF5NOCR 0 R/W 4 PF4NOCR 0 R/W 3 P

Rev. 1.00, 05/04, page 142 of 544 7.14 Port G Port G is an 8-bit I/O port. Port G pins also function as IIC_0 and IIC_1 I/O pins. The output type of

Rev. 1.00, 05/04, page 143 of 544 7.14.2 Port G Output Data Register (PGODR) PGODR stores output data for the pins on port G. Bit Bit Name Initial V

Rev. 1.00, 05/04, page 144 of 544 7.14.4 Pin Functions • PG7/ExSCLB The pin function is switched as shown below according to the combination of the

Rev. 1.00, 05/04, page 145 of 544 • PG3, PG2, PG1, PG0 The pin function is switched as shown below according to the state of the PGnDDR bit. PGnDDR

Rev. 1.00, 05/04, page xviii of xxxiv 14.4.6 KBF Setting Timing and KCLK Control... 362 14

Rev. 1.00, 05/04, page 146 of 544

PWM0800B_000120040200 Rev. 1.00, 05/04, page 147 of 544 Section 8 8-Bit PWM Timer (PWM) This LSI has an on-chip pulse width modulation (PWM) timer

Rev. 1.00, 05/04, page 148 of 544 8.2 Input/Output Pins Table 8.1 shows the PWM output pins. Table 8.1 Pin Configuration Name Abbreviation I/O Funct

Rev. 1.00, 05/04, page 149 of 544 8.3.1 PWM Register Select (PWSL) PWSL is used to select the input clock and the PWM data register. Bit Bit Name

Rev. 1.00, 05/04, page 150 of 544 Table 8.2 Internal Clock Selection PWSL PCSR PWCKE PWCKS PWCKC PWCKB PWCKA Description 0 — — — — Clock inpu

Rev. 1.00, 05/04, page 151 of 544 8.3.2 PWM Data Registers 7 to 0 (PWDR7 to PWD0) PWDR are 8-bit readable/writable registers. The PWM has eight PWM

Rev. 1.00, 05/04, page 152 of 544 8.3.4 PWM Output Enable Register A (PWOERA) PWOERA switches between PWM output and port output. Bit Bit Name Initi

Rev. 1.00, 05/04, page 153 of 544 8.4 Operation The upper four bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolut

Rev. 1.00, 05/04, page 154 of 544 The lower four bits of PWDR specify the position of pulses added to the 16 basic pulses. An additional pulse adds a

Rev. 1.00, 05/04, page 155 of 544 8.4.1 PWM Setting Example : Pulse added1-conversion cycleCombination of the basic pulse and added pulse outputs 0/2

Rev. 1.00, 05/04, page xix of xxxiv 16.4.2 Scan Mode ...

Rev. 1.00, 05/04, page 156 of 544 8.5 Usage Notes 8.5.1 Module Stop Mode Setting PWM operation can be enabled or disabled by the module stop control

TIM8FR1A_010020020700 Rev. 1.00, 05/04, page 157 of 544 Section 9 16-Bit Free-Running Timer (FRT) This LSI has an on-chip 16-bit free-running time

Rev. 1.00, 05/04, page 158 of 544 Figure 9.1 shows a block diagram of the FRT. Clock selectorClockCompare-match AOCRAComparator AInternal data busFRC

Rev. 1.00, 05/04, page 159 of 544 9.2 Input/Output Pins Table 9.1 lists the FRT input and output pins. Table 9.1 Pin Configuration Name Abbreviation

Rev. 1.00, 05/04, page 160 of 544 9.3.1 Free-Running Counter (FRC) FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits

Rev. 1.00, 05/04, page 161 of 544 9.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF) OCRAR and OCRAF are 16-bit readable/writable registers. Wh

Rev. 1.00, 05/04, page 162 of 544 9.3.6 Timer Interrupt Enable Register (TIER) TIER enables and disables interrupt requests. Bit Bit Name Initial Va

Rev. 1.00, 05/04, page 163 of 544 Bit Bit Name Initial Value R/W Description 2 OCIBE 0 R/W Output Compare Interrupt B Enable Selects whether to

Rev. 1.00, 05/04, page 164 of 544 Bit Bit Name Initial Value R/W Description 6 ICFB 0 R/(W)* Input Capture Flag B This status flag indicates that

Rev. 1.00, 05/04, page 165 of 544 Bit Bit Name Initial Value R/W Description 3 OCFA 0 R/(W)* Output Compare Flag A This status flag indicates that

Rev. 1.00, 05/04, page ii of xxxiv

Rev. 1.00, 05/04, page xx of xxxiv 19.2 Duty Correction Circuit ...

Rev. 1.00, 05/04, page 166 of 544 9.3.8 Timer Control Register (TCR) TCR selects the rising or falling edge of the input capture signals, enables th

Rev. 1.00, 05/04, page 167 of 544 Bit Bit Name Initial Value R/W Description 1 0 CKS1 CKS0 0 0 R/W Clock Select 1, 0 Select clock source for FRC.

Rev. 1.00, 05/04, page 168 of 544 Bit Bit Name Initial Value R/W Description 4 OCRS 0 R/W Output Compare Register Select OCRA and OCRB share the

Rev. 1.00, 05/04, page 169 of 544 9.4 Operation 9.4.1 Pulse Output Figure 9.2 shows an example of 50%-duty pulses output with an arbitrary phase diff

Rev. 1.00, 05/04, page 170 of 544 9.5 Operation Timing 9.5.1 FRC Increment Timing Figure 9.3 shows the FRC increment timing with an internal clock s

Rev. 1.00, 05/04, page 171 of 544 9.5.2 Output Compare Output Timing A compare-match signal occurs at the last state when the FRC and OCR values mat

Rev. 1.00, 05/04, page 172 of 544 9.5.4 Input Capture Input Timing The rising or falling edge can be selected for the input capture input timing by

Rev. 1.00, 05/04, page 173 of 544 9.5.5 Buffered Input Capture Input Timing ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Fi

Rev. 1.00, 05/04, page 174 of 544 9.5.6 Timing of Input Capture Flag (ICF) Setting The input capture flag, ICFA, ICFB, ICFC, or ICFD, is set to 1 by

Rev. 1.00, 05/04, page 175 of 544 9.5.8 Timing of FRC Overflow Flag Setting The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from

Rev. 1.00, 05/04, page xxi of xxxiv 22.5 Flash Memory Characteristics ...

Rev. 1.00, 05/04, page 176 of 544 9.5.10 Mask Signal Generation Timing When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other t

Rev. 1.00, 05/04, page 177 of 544 9.6 Interrupt Sources The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each

Rev. 1.00, 05/04, page 178 of 544 9.7.2 Conflict between FRC Write and Increment If an FRC increment pulse is generated during the state after an FR

Rev. 1.00, 05/04, page 179 of 544 φAddress OCR addressInternal write signalCompare-match signalFRCWrite dataDisabledOCR NMNN + 1T1T2Write cycle of OC

Rev. 1.00, 05/04, page 180 of 544 9.7.4 Switching of Internal Clock and FRC Operation When the internal clock is changed, the changeover may cause F

Rev. 1.00, 05/04, page 181 of 544 No. Timing of Switchover by Means of CKS1 and CKS0 Bits FRC Operation 3 Switching from high to low Clock before

Rev. 1.00, 05/04, page 182 of 544

TIMH265B_000020040200 Rev. 1.00, 05/04, page 183 of 544 Section 10 8-Bit Timer (TMR) This LSI has an on-chip 8-bit timer module (TMR_0, TMR_1, TMR

Rev. 1.00, 05/04, page 184 of 544 Table 10.1 TMR Function Item TMR_0 TMR_1 TMR_Y TMR_X TMR_B TMR_A Count clock φ/2 φ/8 φ/32 φ/64 φ/256 φ/1024 φ/2

Rev. 1.00, 05/04, page 185 of 544 Figures 10.1 to 10.3 show block diagrams of 8-bit timers. External clock sourcesInternal clock sourcesTMR_0φ/2, φ/

Rev. 1.00, 05/04, page xxii of xxxiv

Rev. 1.00, 05/04, page 186 of 544 External clock sourcesInternal clocksourcesTMR_Xφ, φ/2, φ/4, φ/2048*, φ/4096*, φ/8192*Clock XClock YCompare-match A

Rev. 1.00, 05/04, page 187 of 544 External clock sourcesInternal clocksourcesTMR_Aφ, φ/2, φ/4, φ/2048, φ/4096, φ/8192Clock AClock BCompare-match AACo

Rev. 1.00, 05/04, page 188 of 544 10.2 Input/Output Pins Table 10.2 summarizes the input and output pins of the TMR. Table 10.2 Pin Configuration Ch

Rev. 1.00, 05/04, page 189 of 544 10.3 Register Descriptions The TMR has the following registers. For details on the serial timer control register, s

Rev. 1.00, 05/04, page 190 of 544 For both TMR_Y and TMR_X Timer XY control register (TCRXY) TMR_B Timer counter_B (TCNT_B) Time constant regi

Rev. 1.00, 05/04, page 191 of 544 10.3.1 Timer Counter (TCNT) Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a singl

Rev. 1.00, 05/04, page 192 of 544 10.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the condition by which TCNT is cleared,

Rev. 1.00, 05/04, page 193 of 544 Table 10.3 Clock Input to TCNT and Count Condition (1) TCR STCR Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description 0

Rev. 1.00, 05/04, page 194 of 544 Table 10.3 Clock Input to TCNT and Count Condition (2) TCR TCRXY*2 Channel CKS2 CKS1 CKS0 CKSX CKSY Descripti

Rev. 1.00, 05/04, page 195 of 544 Table 10.3 Clock Input to TCNT and Count Condition (3) TCR TCRAB Channel CKS2 CKS1 CKS0 CKSA CKSB Description

Rev. 1.00, 05/04, page xxiii of xxxiv Figures Section 1 Overview Figure 1.1 Internal Block Diagram ...

Rev. 1.00, 05/04, page 196 of 544 10.3.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output. TCS

Rev. 1.00, 05/04, page 197 of 544 TCSR_1 Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W)* Compare-Match Flag B [Setting condition] Whe

Rev. 1.00, 05/04, page 198 of 544 TCSR_Y Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W)*1 Compare-Match Flag B [Setting condition] Whe

Rev. 1.00, 05/04, page 199 of 544 TCSR_X Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W)* Compare-Match Flag B [Setting condition] When

Rev. 1.00, 05/04, page 200 of 544 TCSR_B Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W)* Compare-Match Flag B [Setting condition] When

Rev. 1.00, 05/04, page 201 of 544 TCSR_A Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W)* Compare-Match Flag B [Setting condition] When

Rev. 1.00, 05/04, page 202 of 544 10.3.6 Time Constant Register (TCORC) TCORC is an 8-bit readable/writable register. The sum of contents of TCORC a

Rev. 1.00, 05/04, page 203 of 544 10.3.9 Timer Connection Register I (TCONRI) TCONRI controls the input capture function. Bit Bit Name Initial Value

Rev. 1.00, 05/04, page 204 of 544 Table 10.4 Registers Accessible by TMR_X/TMR_Y TMRX/Y H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4

Rev. 1.00, 05/04, page 205 of 544 10.3.12 Timer AB Control Register (TCRAB) TCRAB selects the internal clock or controls the input capture function

Rev. 1.00, 05/04, page xxiv of xxxiv Section 8 8-Bit PWM Timer (PWM) Figure 8.1 Block Diagram of PWM Timer...

Rev. 1.00, 05/04, page 206 of 544 10.4 Operation 10.4.1 Pulse Output Figure 10.4 shows an example for outputting an arbitrary duty pulse. 1. Clear t

Rev. 1.00, 05/04, page 207 of 544 10.5 Operation Timing 10.5.1 TCNT Count Timing Figure 10.5 shows the TCNT count timing with an internal clock sour

Rev. 1.00, 05/04, page 208 of 544 φTCNT NN + 1TCOR NCompare-matchsignalCMF Figure 10.7 Timing of CMF Setting at Compare-Match 10.5.3 Timing of Tim

Rev. 1.00, 05/04, page 209 of 544 10.5.5 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input, depending on the s

Rev. 1.00, 05/04, page 210 of 544 10.6 TMR_0 and TMR_1 Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the

Rev. 1.00, 05/04, page 211 of 544 10.7 TMR_Y and TMR_X Cascaded Connection If bits CKS2 to CKS0 in either TCR_Y or TCR_X are set to B'100, the

Rev. 1.00, 05/04, page 212 of 544 10.7.3 Input Capture Operation TMR_X has input capture registers (TICRR and TICRF). A narrow pulse width can be mea

Rev. 1.00, 05/04, page 213 of 544 10.8.3 Input Capture Operation TMR_A has input capture registers (TICRR_A and TICRF_A). A narrow pulse width can be

Rev. 1.00, 05/04, page 214 of 544 Selection of Input Capture Signal Input: TMRIX (input capture input signal of TMR_X) is selected according to the s

Rev. 1.00, 05/04, page 215 of 544 10.9 Interrupt Sources TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI. TMR_X c

Rev. 1.00, 05/04, page xxv of xxxiv Figure 10.13 Timing of Input Capture Signal (Input capture signal is input during TICRR and TICR

Rev. 1.00, 05/04, page 216 of 544 10.10 Usage Notes 10.10.1 Conflict between TCNT Write and Counter Clear If a counter clear signal is generated duri

Rev. 1.00, 05/04, page 217 of 544 10.10.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T2 state of a TCOR write

Rev. 1.00, 05/04, page 218 of 544 10.10.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is

Rev. 1.00, 05/04, page 219 of 544 No. Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation 3 Clock switching from high to

Rev. 1.00, 05/04, page 220 of 544

WDT0102A_020020040200 Rev. 1.00, 05/04, page 221 of 544 Section 11 Watchdog Timer (WDT) This LSI incorporates two watchdog timer channels (WDT_0 a

Rev. 1.00, 05/04, page 222 of 544 WOVI0 (Interrupt request signal)Internal NMI (Interrupt request signal*2)RESO signal*1Internal reset signal*1TCNT_0

Rev. 1.00, 05/04, page 223 of 544 11.2 Input/Output Pins The WDT has the pins listed in table 11.1. Table 11.1 Pin Configuration Name Symbol I/O Fun

Rev. 1.00, 05/04, page 224 of 544 11.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode.

Rev. 1.00, 05/04, page 225 of 544 Bit Bit Name Initial Value R/W Description 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 Selects the

Rev. 1.00, 05/04, page xxvi of xxxiv Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception ... 270 Figure 12.2

Rev. 1.00, 05/04, page 226 of 544 Bit Bit Name Initial Value R/W Description 4 PSS 0 R/W Prescaler Select Selects the clock source to be input to T

Rev. 1.00, 05/04, page 227 of 544 11.4 Operation 11.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in

Rev. 1.00, 05/04, page 228 of 544 TCNT valueH'00TimeH'FFWT/IT = 1TME = 1Write H'00 toTCNTWT/IT = 1TME = 1Write H'00 toTCNT518 sys

Rev. 1.00, 05/04, page 229 of 544 11.4.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is genera

Rev. 1.00, 05/04, page 230 of 544 11.4.3 RESO Signal Output Timing When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When

Rev. 1.00, 05/04, page 231 of 544 11.6 Usage Notes 11.6.1 Notes on Register Access The watchdog timer's registers, TCNT and TCSR differ from ot

Rev. 1.00, 05/04, page 232 of 544 11.6.2 Conflict between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated durin

Rev. 1.00, 05/04, page 233 of 544 11.6.5 System Reset by RESO Signal Inputting the RESO output signal to the RESO pin of this LSI prevents the LSI f

Rev. 1.00, 05/04, page 234 of 544

SCI0022C_000020020800 Rev. 1.00, 05/04, page 235 of 544 Section 12 Serial Communication Interface (SCI) This LSI has a serial communication interf

Rev. 1.00, 05/04, page xxvii of xxxiv Figure 13.25 IRIC Setting Timing and SCL Control (1) ...

Rev. 1.00, 05/04, page 236 of 544 ExRxD*/RxDExTxD*/TxDExSCK*/SCKClockφφ/4φ/16φ/64TEITXIRXIERISCMRSSRSCRSMRTransmission/reception controlBaud rategene

Rev. 1.00, 05/04, page 237 of 544 12.3 Register Descriptions The SCI has the following registers. • Receive shift register (RSR) • Receive data reg

Rev. 1.00, 05/04, page 238 of 544 12.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data tr

Rev. 1.00, 05/04, page 239 of 544 Bit Bit Name Initial Value R/W Description 2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous mode)

Rev. 1.00, 05/04, page 240 of 544 Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the

Rev. 1.00, 05/04, page 241 of 544 12.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits f

Rev. 1.00, 05/04, page 242 of 544 Bit Bit Name Initial Value R/W Description 3 PER 0 R/(W)* Parity Error [Setting condition] • When a parity erro

Rev. 1.00, 05/04, page 243 of 544 12.3.8 Serial Interface Mode Register (SCMR) SCMR selects SCI functions and its format. Bit Bit Name Initial Value

Rev. 1.00, 05/04, page 244 of 544 12.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate g

Rev. 1.00, 05/04, page 245 of 544 Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 4 4.9152 5

Rev. 1.00, 05/04, page xxviii of xxxiv Section 16 A/D Converter Figure 16.1 Block Diagram of A/D Converter ...

Rev. 1.00, 05/04, page 246 of 544 Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 6 6.144 7.3728

Rev. 1.00, 05/04, page 247 of 544 Table 12.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N φ (MHz) Ma

Rev. 1.00, 05/04, page 248 of 544 Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) 4 8 10 Bit Ra

Rev. 1.00, 05/04, page 249 of 544 12.3.10 Serial Pin Select Register (SPSR) SPSR selects the serial I/O pins. SPSR should be set before initializati

Rev. 1.00, 05/04, page 250 of 544 12.4.1 Data Transfer Format Table 12.8 shows the data transfer formats that can be used in asynchronous mode. Any

Rev. 1.00, 05/04, page 251 of 544 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operat

Rev. 1.00, 05/04, page 252 of 544 12.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at th

Rev. 1.00, 05/04, page 253 of 544 12.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE

Rev. 1.00, 05/04, page 254 of 544 12.4.5 Data Transmission (Asynchronous Mode) Figure 12.6 shows an example of the operation for transmission in asy

Rev. 1.00, 05/04, page 255 of 544 No<End>[1]YesInitializationStart transmissionRead TDRE flag in SSR [2]Write transmit data to TDRand clear TDR

Rev. 1.00, 05/04, page xxix of xxxiv Figure 22.4 Connection of VCL Capacitor...

Rev. 1.00, 05/04, page 256 of 544 12.4.6 Serial Data Reception (Asynchronous Mode) Figure 12.8 shows an example of the operation for reception in as

Rev. 1.00, 05/04, page 257 of 544 Table 12.9 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* ORER FER PER Receive Data Receive E

Rev. 1.00, 05/04, page 258 of 544 <End>[3]Error processingParity error processingYesNoClear ORER, PER, andFER flags in SSR to 0NoYesNoYesFramin

Rev. 1.00, 05/04, page 259 of 544 12.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer

Rev. 1.00, 05/04, page 260 of 544 12.5.1 Multiprocessor Serial Data Transmission Figure 12.11 shows a sample flowchart for multiprocessor serial data

Rev. 1.00, 05/04, page 261 of 544 12.5.2 Multiprocessor Serial Data Reception Figure 12.13 shows a sample flowchart for multiprocessor serial data re

Rev. 1.00, 05/04, page 262 of 544 Yes<End>[1]NoInitializationStart receptionNoYes[4]Clear RE bit in SCR to 0Error processing(Continued onnext p

Rev. 1.00, 05/04, page 263 of 544 <End>Error processingYesNoClear ORER, PER, andFER flags in SSR to 0NoYesNoYesFraming error processingOverrun

Rev. 1.00, 05/04, page 264 of 544 12.6 Operation in Clocked Synchronous Mode Figure 12.14 shows the general format for clocked synchronous communica

Rev. 1.00, 05/04, page 265 of 544 12.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clea

Rev. 1.00, 05/04, page iii of xxxiv 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology

Rev. 1.00, 05/04, page xxx of xxxiv

Rev. 1.00, 05/04, page 266 of 544 12.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 12.16 shows an example of SCI operation for tran

Rev. 1.00, 05/04, page 267 of 544 No<End>[1]YesInitializationStart transmissionRead TDRE flag in SSR [2]Write transmit data to TDR andclear TDR

Rev. 1.00, 05/04, page 268 of 544 12.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 12.18 shows an example of SCI operation for recepti

Rev. 1.00, 05/04, page 269 of 544 Yes<End>[1]NoInitializationStart reception[2]NoYesRead RDRF flag in SSR [4][5]Clear RE bit in SCR to 0Error p

Rev. 1.00, 05/04, page 270 of 544 Yes<End>[1]NoInitializationStart transmission/reception[5]Error processing[3]Read receive data in RDR, andcle

Rev. 1.00, 05/04, page 271 of 544 12.7 Interrupt Sources Table 12.10 shows the interrupt sources in serial communication interface. A different inter

Rev. 1.00, 05/04, page 272 of 544 12.8 Usage Notes 12.8.1 Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop con

Rev. 1.00, 05/04, page 273 of 544 12.8.6 SCI Operations during Mode Transitions Transmission: Before making a transition to module stop, software st

Rev. 1.00, 05/04, page 274 of 544 Start transmissionTransmission[1]NoNoNoYesYesYesRead TEND flag in SSRMake transition to software standby mode etc.C

Rev. 1.00, 05/04, page 275 of 544 TE bitSCK output pinTxD output pinPort input/outputPort input/outputPort input/outputHigh output*Marking outputTran

Rev. 1.00, 05/04, page xxxi of xxxiv Tables Section 1 Overview Table 1.1 Pin Functions in Each Operating Mode ...

Rev. 1.00, 05/04, page 276 of 544 12.8.7 Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has complet

IFIIC60B_010020040200 Rev. 1.00, 05/04, page 277 of 544 Section 13 I2C Bus Interface (IIC) This LSI has a two-channel I2C bus interface. The I2C b

Rev. 1.00, 05/04, page 278 of 544 • Selectable input/output pins*  Pins, PG4/ExSDAA, PG5/ExSCLA, PG6/ExSDAB, and PG7/ExSCLB, are selectable for th

Rev. 1.00, 05/04, page 279 of 544 SCL inSCL outSDA inSDA out(Slave 1)SCLSDASCL inSCL outSDA inSDA out(Slave 2)SCLSDASCL inSCL outSDA inSDA out(Master

Rev. 1.00, 05/04, page 280 of 544 13.2 Input/Output Pins Table 13.1 summarizes the input/output pins used by the I2C bus interface. The serial clock

Rev. 1.00, 05/04, page 281 of 544 13.3 Register Descriptions The I2C bus interface has the following registers. Registers ICDR and SARX and registers

Rev. 1.00, 05/04, page 282 of 544 13.3.1 I2C Bus Data Register (ICDR) ICDR is an 8-bit readable/writable register that is used as a transmit data reg

Rev. 1.00, 05/04, page 283 of 544 13.3.2 Slave Address Register (SAR) SAR sets the slave address and selects the communication format. If the LSI is

Rev. 1.00, 05/04, page 284 of 544 13.3.3 Second Slave Address Register (SARX) SARX sets the second slave address and selects the communication forma

Rev. 1.00, 05/04, page 285 of 544 Table 13.2 Communication Format SAR SARX FS FSX Operating Mode 0 0 I2C bus format • SAR and SARX slave addresse

Rev. 1.00, 05/04, page xxxii of xxxiv Table 7.4 Input Pull-Up MOS States (Port 3)...

Rev. 1.00, 05/04, page 286 of 544 13.3.4 I2C Bus Mode Register (ICMR) ICMR sets the communication format and transfer rate. It can only be accessed w

Rev. 1.00, 05/04, page 287 of 544 Bit Bit Name Initial Value R/W Description 2 1 0 BC2 BC1 BC0 0 0 0 R/W R/W R/W Bit Counter 2 to 0 These bits speci

Rev. 1.00, 05/04, page 288 of 544 Table 13.3 I2C Transfer Rate STCR ICMR Bits 5 and 6 Bit 5 Bit 4 Bit 3 Transfer Rate IICX CKS2 CKS1 CKS0

Rev. 1.00, 05/04, page 289 of 544 13.3.5 I2C Bus Control Register (ICCR) ICCR controls the I2C bus interface and performs interrupt flag confirmation

Rev. 1.00, 05/04, page 290 of 544 Bit Bit Name Initial Value R/W Description 5 4 MST TRS 0 0 R/W [MST clearing conditions] 1. When 0 is written by

Rev. 1.00, 05/04, page 291 of 544 Bit Bit Name Initial Value R/W Description 2 0 BBSY SCP 0 1 R/W* W Bus Busy Start Condition/Stop Condition Prohibi

Rev. 1.00, 05/04, page 292 of 544 Bit Bit Name Initial Value R/W Description 1 IRIC 0 R/(W)* I2C Bus Interface Interrupt Request Flag Indicates that

Rev. 1.00, 05/04, page 293 of 544 Bit Bit Name Initial Value R/W Description 1 IRIC 0 R/(W)* Clocked synchronous serial format mode: • At the en

Rev. 1.00, 05/04, page 294 of 544 Table 13.4 Flags and Transfer States (Master Mode) MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICD

Rev. 1.00, 05/04, page 295 of 544 Table 13.5 Flags and Transfer States (Slave Mode) MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDR

Rev. 1.00, 05/04, page xxxiii of xxxiv Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) ... 248 Table 12.8 Serial

Rev. 1.00, 05/04, page 296 of 544 Table 13.5 Flags and Transfer States (Slave Mode) (cont) MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICD

Rev. 1.00, 05/04, page 297 of 544 13.3.6 I2C Bus Status Register (ICSR) ICSR consists of status flags. Also see tables 13.4 and 13.5. Bit Bit Name In

Rev. 1.00, 05/04, page 298 of 544 Bit Bit Name Initial Value R/W Description 4 AASX 0 R/(W)* Second Slave Address Recognition Flag In I2C bus form

Rev. 1.00, 05/04, page 299 of 544 Bit Bit Name Initial Value R/W Description 2 AAS 0 R/(W)* Slave Address Recognition Flag In I2C bus format slav

Rev. 1.00, 05/04, page 300 of 544 Bit Bit NameInitial Value R/W Description 0 ACKB 0 R/W Acknowledge Bit Stores acknowledge data. Transmit mode: [S

Rev. 1.00, 05/04, page 301 of 544 13.3.7 DDC Switch Register (DDCSWR) DDCSWR controls IIC internal latch clearance. Bit Bit Name Initial Value R/W

Rev. 1.00, 05/04, page 302 of 544 13.3.8 I2C Bus Extended Control Register (ICXR) ICXR enables or disables the I2C bus interface interrupt generation

Rev. 1.00, 05/04, page 303 of 544 Bit Bit Name Initial Value R/W Description 5 ICDRF 0 R Receive Data Read Request Flag Indicates the ICDR (ICDR

Rev. 1.00, 05/04, page 304 of 544 Bit Bit NameInitial Value R/W Description 4 ICDRE 0 R Transmit Data Write Request Flag Indicates the ICDR (ICD

Rev. 1.00, 05/04, page 305 of 544 Bit Bit Name Initial Value R/W Description 3 ALIE 0 R/W Arbitration Lost Interrupt Enable Enables or disables

Rev. 1.00, 05/04, page xxxiv of xxxiv Section 19 Clock Pulse Generator Table 19.1 Damping Resistance Values ...

Rev. 1.00, 05/04, page 306 of 544 13.3.9 Port G Control Register (PGCTL) PGCTL selects the input/output pin for IIC. Bit Bit Name Initial Value R/W

Rev. 1.00, 05/04, page 307 of 544 13.4 Operation The I2C bus interface has an I2C bus format and a serial format. 13.4.1 I2C Bus Data Format The I2C

Rev. 1.00, 05/04, page 308 of 544 SDASCLS SLA R/W A981 to 7 981 to 7 981 to 7DATA A DATA A/AP Figure 13.5 I2C Bus Timing Table 13.6 I2C Bus Data F

Rev. 1.00, 05/04, page 309 of 544 13.4.2 Initialization Initialize the IIC by the procedure shown in figure 13.6 before starting transmission/recepti

Rev. 1.00, 05/04, page 310 of 544 StartInitialize IICSet MST = 1 and TRS = 1 in ICCRSet BBSY =1 and SCP = 0 in ICCRWrite transmit data in ICDRClear I

Rev. 1.00, 05/04, page 311 of 544 The transmission procedure and operations by which data is sequentially transmitted in synchronization with ICDR (I

Rev. 1.00, 05/04, page 312 of 544 12. Clear the IRIC flag to 0. Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SC

Rev. 1.00, 05/04, page 313 of 544 SDA(master output)SDA(slave output)21436587989ABit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Bit 0ICDREIRTRICDRSCL

Rev. 1.00, 05/04, page 314 of 544 13.4.4 Master Receive Operation In I2C bus format master receive mode, the master device outputs the receive clock,

Rev. 1.00, 05/04, page 315 of 544 The reception procedure and operations using the HNDS function, by which the data reception process is provided in

Rev. 1.00, 05/04, page 1 of 544 Section 1 Overview 1.1 Features • High-speed H8S/2000 central processing unit with an internal 16-bit architecture

Rev. 1.00, 05/04, page 316 of 544 SDA(master output)SDA(slave output)214365871299AABit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Bit 7Bit 6IRTRICDRFICDRRSC

Rev. 1.00, 05/04, page 317 of 544 Receive Operation Using the Wait Function: Figures 13.13 and 13.14 show the sample flowcharts for the operations in

Rev. 1.00, 05/04, page 318 of 544 EndSet HNDS = 0 in ICXR Set WAIT = 0 in ICMR Set WAIT = 0 in ICMRSet ACKB = 0 in ICSRSet ACKB = 1 in ICSRRead ICDRC

Rev. 1.00, 05/04, page 319 of 544 The reception procedure and operations using the wait function (WAIT bit), by which data is sequentially received i

Rev. 1.00, 05/04, page 320 of 544 12. The IRIC flag is set to 1 in either of the following cases.  At the fall of the 8th receive clock pulse for o

Rev. 1.00, 05/04, page 321 of 544 SDA(master output)SDA(slave output)21436587998AABit 7Bit 0Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1IRICIRTRICDRSCL(master outp

Rev. 1.00, 05/04, page 322 of 544 Slave receive modeEndRead IRIC flag in ICCRClear IRIC flag in ICCRRead IRIC flag in ICCRRead AASX, AAS and ADZ in I

Rev. 1.00, 05/04, page 323 of 544 The reception procedure and operations using the HNDS bit function, by which data reception process is provided in

Rev. 1.00, 05/04, page 324 of 544 SDA(master output)SDA(slave output)21 214365879Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0ICDRFIRICI

Rev. 1.00, 05/04, page 325 of 544 Continuous Receive Operation: Figure 13.20 shows the sample flowchart for the operations in slave receive mode (HND

Rev. 1.00, 05/04, page 2 of 544 1.2 Internal Block Diagram P17/PW7P16/PW6P15/PW5P14/PW4P13/PW3P12/PW2P11/PW1P10/PW0P27 P26P25P24P23P22P21P20PA7/KIN1

Rev. 1.00, 05/04, page 326 of 544 The reception procedure and operations in slave receive are described below. 1. Initialize the IIC as described in

Rev. 1.00, 05/04, page 327 of 544 SDA(master output)SDA(slave output)2143214365879Bit 7 Bit 6Bit 7Bit 6Bit 5Bit 4Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0I

Rev. 1.00, 05/04, page 328 of 544 13.4.6 Slave Transmit Operation If the slave address matches to the address in the first frame (address reception

Rev. 1.00, 05/04, page 329 of 544 In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clo

Rev. 1.00, 05/04, page 330 of 544 10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL is high, the BBSY f

Rev. 1.00, 05/04, page 331 of 544 13.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on

Rev. 1.00, 05/04, page 332 of 544 SCLSDAIRICUser processingClear IRIC213A812398Clear IRICWhen WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait i

Rev. 1.00, 05/04, page 333 of 544 SCLSDAIRICUser processingClear IRIC187412387When FS = 1 and FSX = 1 (clocked synchronous serial format)(a) Data tr

Rev. 1.00, 05/04, page 334 of 544 13.4.8 Noise Canceller The logic levels at the SCL and SDA pins are routed through noise cancellers before being la

Rev. 1.00, 05/04, page 335 of 544 13.4.9 Initialization of Internal State The IIC has a function for forcible initialization of its internal state i

Rev. 1.00, 05/04, page 3 of 544 1.3 Pin Description 1.3.1 Pin Arrangement 727170696867666564636261605958575655545352515049484746454443424140393837109

Rev. 1.00, 05/04, page 336 of 544 The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition p

Rev. 1.00, 05/04, page 337 of 544 13.6 Usage Notes 1. In master mode, if an instruction to generate a start condition is issued and then an instruct

Rev. 1.00, 05/04, page 338 of 544 5. The I2C bus interface specification for the SCL rise time tsr is 1000 ns or less (300 ns for high-speed mode). I

Rev. 1.00, 05/04, page 339 of 544 Table 13.10 I2C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] Ite

Rev. 1.00, 05/04, page 340 of 544 7. Notes on ICDR read at end of master reception To halt reception at the end of a receive operation in master rec

Rev. 1.00, 05/04, page 341 of 544 8. Notes on start condition issuance for retransmission Figure 13.30 shows the timing of start condition issuance

Rev. 1.00, 05/04, page 342 of 544 9. Note on when I2C bus interface stop condition instruction is issued In cases where the rise time of the 9th clo

Rev. 1.00, 05/04, page 343 of 544 10. Note on IRIC flag clear when the wait function is used If the rise time of SCL exceeds the stipulated value or

Rev. 1.00, 05/04, page 344 of 544 11. Note on ICDR read and ICCR access in slave transmit mode In I2C bus interface slave transmit mode, do not read

Rev. 1.00, 05/04, page 345 of 544 12. Note on TRS bit setting in slave mode In I2C bus interface slave mode, if the TRS bit value in ICCR is set afte

Rev. 1.00, 05/04, page 4 of 544 1.3.2 Pin Functions in Each Operating Mode Table 1.1 Pin Functions in Each Operating Mode Pin Name Pin No. Sing

Rev. 1.00, 05/04, page 346 of 544 13. Note on ICDR read in transmit mode and ICDR write in receive mode If ICDR is read in transmit mode (TRS = 1) or

Rev. 1.00, 05/04, page 347 of 544 SASLAR/WSASLAR/W ADATA2SASLAR/W ASLAR/WADATA3ADATA4DATA1I2C bus interface(Master transmit mode)Transmit data matchT

Rev. 1.00, 05/04, page 348 of 544

IFKEY10A_000020020700 Rev. 1.00, 05/04, page 349 of 544 Section 14 Keyboard Buffer Controller This LSI has three on-chip keyboard buffer controlle

Rev. 1.00, 05/04, page 350 of 544 Figure 14.2 shows how the keyboard buffer controller is connected. VccKCLK inKCLK outKD inKD outKeyboard buffer con

Rev. 1.00, 05/04, page 351 of 544 14.3 Register Descriptions The keyboard buffer controller has the following registers for each channel. • Keyboard

Rev. 1.00, 05/04, page 352 of 544 Bit Bit Name Initial Value R/W Description 3 KBIE 0 R/W Keyboard Interrupt Enable Enables or disables interrup

Rev. 1.00, 05/04, page 353 of 544 14.3.2 Keyboard Control Register L (KBCRL) KBCRL enables the receive counter count and controls the keyboard buffe

Rev. 1.00, 05/04, page 354 of 544 14.3.3 Keyboard Data Buffer Register (KBBR) KBBR stores receive data. Its value is valid only when KBF = 1. Bit Bi

Rev. 1.00, 05/04, page 355 of 544 14.4 Operation 14.4.1 Receive Operation In a receive operation, both KCLK (clock) and KD (data) are outputs on the

Rev. 1.00, 05/04, page 5 of 544 Pin Name Pin No. Single-Chip Modes Flash Memory TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode 31 P

Rev. 1.00, 05/04, page 356 of 544 123KCLK (pin state)KD (pin state)KCLK (input)KCLK (output)KB7 to KB0PERKBSKBFStart bitParity bitStop bitReceive pro

Rev. 1.00, 05/04, page 357 of 544 StartSet KBIOE bitKCLKI = 0?Read KBCRHKCLKIand KDI bits both1?Set I/O inhibit (KCLKO = 0)KBE = 0 (KBBR reception pr

Rev. 1.00, 05/04, page 358 of 544 Read KBCRHTransmit end state(KCLK = high, KD = high)YesNote: * To switch to reception after transmission, set KBE

Rev. 1.00, 05/04, page 359 of 544 14.4.3 Receive Abort This LSI (system side) can forcibly abort transmission from the device connected to it (keyboa

Rev. 1.00, 05/04, page 360 of 544 Receive data processingClear KBF flag(KCLK = High)Processing 1Receive operation endsnormally[1] On the system side

Rev. 1.00, 05/04, page 361 of 544 14.4.4 KCLKI and KDI Read Timing Figure 14.9 shows the KCLKI and KDI read timing. T1T2φ*Internal readsignalKCLK, K

Rev. 1.00, 05/04, page 362 of 544 14.4.6 KBF Setting Timing and KCLK Control Figure 14.11 shows the KBF setting timing and the KCLK pin states. KCLK

Rev. 1.00, 05/04, page 363 of 544 14.4.7 Receive Timing Figure 14.12 shows the receive timing. N + 1 N + 2NKCLK (pin)Note: * The φ clock shown here

Rev. 1.00, 05/04, page 364 of 544 14.4.8 KCLK Fall Interrupt Operation In this device, clearing the KBFSEL bit to 0 in KBCRH enables the KBF bit in K

Rev. 1.00, 05/04, page 365 of 544 14.5 Usage Notes 14.5.1 KBIOE Setting and KCLK Falling Edge Detection When KBIOE is 0, the internal KCLK and inter

Rev. 1.00, 05/04, page iv of xxxiv General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins.

Rev. 1.00, 05/04, page 6 of 544 Pin Name Pin No. Single-Chip Modes Flash Memory TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode 61 P

Rev. 1.00, 05/04, page 366 of 544 14.5.2 Module Stop Mode Setting Keyboard buffer controller operation can be enabled or disabled using the module st

IFHSTL0A_020020040200 Rev. 1.00, 05/04, page 367 of 544 Section 15 Host Interface (LPC) This LSI has an on-chip LPC interface. The LPC performs se

Rev. 1.00, 05/04, page 368 of 544 Figure 15.1 shows a block diagram of the LPC. TWR1–15IDR3IDR2IDR1H'0060/64H'0062/66LADR3SIRQCR0SIRQCR1TWR

Rev. 1.00, 05/04, page 369 of 544 15.2 Input/Output Pins Table 15.1 lists the input and output pins of the LPC module. Table 15.1 Pin Configuration

Rev. 1.00, 05/04, page 370 of 544 15.3 Register Descriptions The LPC has the following registers. • Host interface control register 0 (HICR0) • Ho

Rev. 1.00, 05/04, page 371 of 544 15.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1) HICR0 and HICR1 contain control bits that enable or

Rev. 1.00, 05/04, page 372 of 544 R/W Bit Bit Name Initial Value Slave Host Description 4 FGA20E 0 R/W — Fast A20 Gate Function Enable Enables o

Rev. 1.00, 05/04, page 373 of 544 R/W Bit Bit Name Initial Value Slave Host Description 2 PMEE 0 R/W — PME output Enable Controls PME output in

Rev. 1.00, 05/04, page 374 of 544 • HICR1 R/W Bit Bit Name Initial Value Slave Host Description 7 LPCBSY 0 R/W — LPC Busy Indicates that the host in

Rev. 1.00, 05/04, page 375 of 544 R/W Bit Bit Name Initial Value Slave Host Description 5 IRQBSY 0 R — SERIRQ Busy Indicates that the host interface&

Rev. 1.00, 05/04, page 7 of 544 Pin Name Pin No. Single-Chip Modes Flash Memory TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode 91 P

Rev. 1.00, 05/04, page 376 of 544 R/W Bit Bit Name Initial Value Slave Host Description 3 SDWNB 0 R/W — LPC Software Shutdown Bit Controls host

Rev. 1.00, 05/04, page 377 of 544 15.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3) Bits 6 to 0 in HICR2 control interrupts from the ho

Rev. 1.00, 05/04, page 378 of 544 R/W Bit Bit Name Initial Value Slave Host Description 3 IBFIE3 0 R/W — IDR3 and TWR Receive Completion Interrupt

Rev. 1.00, 05/04, page 379 of 544 15.3.3 LPC Channel 3 Address Register (LADR3) LADR3 comprises two 8-bit readable/writable registers that perform L

Rev. 1.00, 05/04, page 380 of 544 Table 15.2 Register Selection I/O Address Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer Cycle Host Register Selectio

Rev. 1.00, 05/04, page 381 of 544 15.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3) The ODR registers are 8-bit readable/writable registers for the

Rev. 1.00, 05/04, page 382 of 544 I/O Address Bits 15 to 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer Cycle Host Register Selection 0000 0000 0110 0 1

Rev. 1.00, 05/04, page 383 of 544 • STR2 R/W Bit Bit Name Initial Value Slave Host Description 7 6 5 4 DBU27 DBU26 DBU25 DBU24 0 0 0 0 R/W R/W R/

Rev. 1.00, 05/04, page 384 of 544 • STR3 (TWRE = 1 or SELSTR3 = 0) R/W Bit Bit Name Initial Value Slave HostDescription 7 IBF3B 0 R R Bidirecti

Rev. 1.00, 05/04, page 385 of 544 R/W Bit Bit Name Initial Value Slave Host Description 3 C/D3 0 R R Command/Data When the host processor writes to a

Rev. 1.00, 05/04, page 8 of 544 Pin Name Pin No. Single-Chip Modes Flash Memory TFP-144 Mode 2, Mode 3 (EXPE = 0) Programmer Mode 121

Rev. 1.00, 05/04, page 386 of 544 • STR3 (TWRE = 0 and SELSTR3 = 1) R/W Bit Bit Name Initial Value Slave Host Description 7 6 5 4 DBU37 DBU36 DBU35

Rev. 1.00, 05/04, page 387 of 544 15.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1) The SIRQCR registers contain status bits that indicate

Rev. 1.00, 05/04, page 388 of 544 R/W Bit Bit Name Initial Value Slave Host Description 4 SMIE3B 0 R/W — Host SMI Interrupt Enable 3B Enables or

Rev. 1.00, 05/04, page 389 of 544 R/W Bit Bit Name Initial Value Slave Host Description 2 SMIE2 0 R/W — Host SMI Interrupt Enable 2 Enables or d

Rev. 1.00, 05/04, page 390 of 544 R/W Bit Bit Name Initial Value Slave Host Description 0 IRQ1E1 0 R/W — Host IRQ1 Interrupt Enable 1 Enables o

Rev. 1.00, 05/04, page 391 of 544 R/W Bit Bit Name Initial Value Slave Host Description 6 IRQ10E3 0 R/W — Host IRQ10 Interrupt Enable 3 Enables

Rev. 1.00, 05/04, page 392 of 544 R/W Bit Bit Name Initial Value Slave Host Description 4 IRQ6E3 0 R/W — Host IRQ6 Interrupt Enable 3 Enables o

Rev. 1.00, 05/04, page 393 of 544 R/W Bit Bit Name Initial Value Slave Host Description 2 IRQ10E2 0 R/W — Host IRQ10 Interrupt Enable 2 Enables

Rev. 1.00, 05/04, page 394 of 544 R/W Bit Bit Name Initial Value Slave Host Description 0 IRQ6E2 0 R/W — Host IRQ6 Interrupt Enable 2 Enables or

Rev. 1.00, 05/04, page 395 of 544 15.3.9 Host Interface Select Register (HISEL) HISEL selects the function of bits 7 to 4 in STR3 and specifies the

Rev. 1.00, 05/04, page 9 of 544 1.3.3 Pin Functions Table 1.2 Pin Functions Pin No. Type Symbol TFP-144 I/O Name and Function VCC 1, 86 Input

Rev. 1.00, 05/04, page 396 of 544 15.4 Operation 15.4.1 Host Interface Activation The host interface is activated by setting one of bits LPC3E to LP

Rev. 1.00, 05/04, page 397 of 544 15.4.2 LPC I/O Cycles There are ten kinds of LPC transfer cycle: memory read, memory write, I/O read, I/O write, D

Rev. 1.00, 05/04, page 398 of 544 The timing of the LFRAME, LCLK, and LAD signals is shown in figures 15.2 and 15.3. ADDRStartLFRAMELAD3–LAD0Number o

Rev. 1.00, 05/04, page 399 of 544 Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1 command followed by dat

Rev. 1.00, 05/04, page 400 of 544 Table 15.4 Fast A20 Gate Output Signals HA0 Data/Command Internal CPU Interrupt Flag (IBF) GA20 (P81) Remarks 1

Rev. 1.00, 05/04, page 401 of 544 15.4.4 Host Interface Shutdown Function (LPCPD) The host interface can be placed in the shutdown state according t

Rev. 1.00, 05/04, page 402 of 544 Table 15.5 shows the scope of the host interface pin shutdown. Table 15.5 Scope of Host Interface Pin Shutdown Abb

Rev. 1.00, 05/04, page 403 of 544 The scope of the initialization in each mode is shown in table 15.6. Table 15.6 Scope of Initialization in Each Ho

Rev. 1.00, 05/04, page 404 of 544 Figure 15.5 shows the timing of the LPCPD and LRESET signals. LPCPDLRESETLAD3–LAD0LFRAMELCLKAt least 30 µsAt least

Rev. 1.00, 05/04, page 405 of 544 15.4.5 Host Interface Serialized Interrupt Operation (SERIRQ) A host interrupt request can be issued from the host

Rev. 1.00, 05/04, page 10 of 544 Pin No. Type Symbol TFP-144 I/O Name and Function FTCI 78 Input The counter clock input pin. FTOA 79 Output

Rev. 1.00, 05/04, page 406 of 544 Serial Interrupt Transfer Cycle Frame Count Contents Drive Source Number of States Notes 0 Start Slave Host 6

Rev. 1.00, 05/04, page 407 of 544 15.4.6 Host Interface Clock Start Request (CLKRUN) A request to restart the clock (LCLK) can be sent to the host p

Rev. 1.00, 05/04, page 408 of 544 15.5 Interrupt Sources 15.5.1 IBFI1, IBFI2, IBFI3, and ERRI The host interface has four interrupt requests for the

Rev. 1.00, 05/04, page 409 of 544 Table 15.8 summarizes the methods of setting and clearing these bits, and figure 15.8 shows the processing flowchar

Rev. 1.00, 05/04, page 410 of 544 Slave CPU Master CPUODR1 writeWrite 1 to IRQ1E1OBF1 = 0?YesNoNoYesAll bytestransferred?SERIRQ IRQ1 outputSERIRQ IRQ

Rev. 1.00, 05/04, page 411 of 544 15.6 Usage Notes 15.6.1 Module Stop Mode Setting LPC operation can be enabled or disabled using the module stop con

Rev. 1.00, 05/04, page 412 of 544 Table 15.9 Host Address Example Register Host Address when LADR3 = H'A24F Host Address when LADR3 = H'3

ADCMS33B_010020040200 Rev. 1.00, 05/04, page 413 of 544 Section 16 A/D Converter This LSI includes a successive-approximation-type 10-bit A/D conv

Rev. 1.00, 05/04, page 414 of 544 A block diagram of the A/D converter is shown in figure 16.1. Module data busControl circuitInternal data bus10-bit

Rev. 1.00, 05/04, page 415 of 544 16.2 Input/Output Pins Table 16.1 summarizes the pins used by the A/D converter. The 6 analog input pins are divide

Rev. 1.00, 05/04, page 11 of 544 Pin No. Type Symbol TFP-144 I/O Name and Function LAD3 to LAD0 124 to 121 Input/ Output LPC command, address, a

Rev. 1.00, 05/04, page 416 of 544 16.3 Register Descriptions The A/D converter has the following registers. • A/D data register A (ADDRA) • A/D dat

Rev. 1.00, 05/04, page 417 of 544 16.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit Bit Name Initial Value R/

Rev. 1.00, 05/04, page 418 of 544 Bit Bit NameInitial Value R/W Description Channel Select 2 to 0 Select analog input channels. The input channel s

Rev. 1.00, 05/04, page 419 of 544 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating

Rev. 1.00, 05/04, page 420 of 544 Figure 16.2 shows the operation timing. 1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), a

Rev. 1.00, 05/04, page 421 of 544 16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D co

Rev. 1.00, 05/04, page 422 of 544 Table 16.3 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol Min. Typ. Max. Min. Typ. Max. A/D conv

Rev. 1.00, 05/04, page 423 of 544 16.5 Interrupt Sources The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversi

Rev. 1.00, 05/04, page 424 of 544 H'001H'00011024210241022102410231024FSQuantization errorDigital outputIdeal A/D conversioncharacteristicA

Rev. 1.00, 05/04, page 425 of 544 16.7 Usage Notes 16.7.1 Permissible Signal Source Impedance This LSI's analog input (3-V version) is designed

Rev. 1.00, 05/04, page 12 of 544 Pin No. Type Symbol TFP-144 I/O Name and Function I2C bus interface (IIC) SCL0 SCL1 ExSCLA* ExSCLB* 14 135 53 51

Rev. 1.00, 05/04, page 426 of 544 16.7.3 Setting Range of Analog Power Supply and Other Pins If conditions shown below are not met, the reliability

Rev. 1.00, 05/04, page 427 of 544 AVCC*1AN0 to AN5AVSSNotes: Values are reference values.2. Rin: Input impedance1.*1Rin*2100 Ω0.1 µF0.01 µF10 µFAVr

Rev. 1.00, 05/04, page 428 of 544

Rev. 1.00, 05/04, page 429 of 544 Section 17 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bu

Rev. 1.00, 05/04, page 430 of 544

ROMF360A_010020040200 Rev. 1.00, 05/04, page 431 of 544 Section 18 ROM This LSI has an on-chip ROM (flash memory). The features of the flash memor

Rev. 1.00, 05/04, page 432 of 544 • Programmer mode In addition to on-board programming mode, programmer mode is supported to program or erase the f

Rev. 1.00, 05/04, page 433 of 544 18.2 Mode Transitions When the mode pins are set in the reset state and a reset-start is executed, this LSI enters

Rev. 1.00, 05/04, page 434 of 544 <Flash memory><This LSI><RAM><Host>Programming control programSCIApplication program (old v

Rev. 1.00, 05/04, page 435 of 544 <Flash memory><This LSI><RAM><Host>Programming/erase control programSCIBoot programNew appl

CPU210A_020020040200 Rev. 1.00, 05/04, page 13 of 544 Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-b

Rev. 1.00, 05/04, page 436 of 544 18.3 Block Configuration Figure 18.5 shows the block configuration of flash memory. The thick lines indicate erasin

Rev. 1.00, 05/04, page 437 of 544 18.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 18.2. Table 18.2 Pin Con

Rev. 1.00, 05/04, page 438 of 544 18.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1, used together with FLMCR2, makes the flash memory transit

Rev. 1.00, 05/04, page 439 of 544 18.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 monitors the state of flash memory programming/erasing prot

Rev. 1.00, 05/04, page 440 of 544 18.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) EBR1 and EBR2 are used to specify the flash memory erase block.

Rev. 1.00, 05/04, page 441 of 544 18.6 Operating Modes The flash memory is connected to the CPU via a 16-bit data bus, enabling byte data and word da

Rev. 1.00, 05/04, page 442 of 544 18.7.1 Boot Mode Table 18.5 shows the boot mode operations between reset end and branching to the programming contr

Rev. 1.00, 05/04, page 443 of 544 7. Boot mode can be cleared by a reset. Cancel the reset*2 after driving the reset pin low, waiting at least 20 st

Rev. 1.00, 05/04, page 444 of 544 Table 18.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate Syst

Rev. 1.00, 05/04, page 445 of 544 18.7.2 User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in

Rev. 1.00, 05/04, page 14 of 544 • Two CPU operating modes Normal mode Advanced mode • Power-down state Transition to power-down state by SLEEP ins

Rev. 1.00, 05/04, page 446 of 544 18.8 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash mem

Rev. 1.00, 05/04, page 447 of 544 STARTEnd of programmingSet SWE bit in FLMCR1Start of programmingWrite pulse application subroutineWait (x) µsSub-Ro

Rev. 1.00, 05/04, page 448 of 544 18.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 18.10 should

Rev. 1.00, 05/04, page 449 of 544 End of erasingSTARTSet SWE bit in FLMCR1Set ESU bit in FLMCR2Set E bit in FLMCR1Wait (x) µsWait (y) µsn = 1Set EBR1

Rev. 1.00, 05/04, page 450 of 544 18.9 Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection,

Rev. 1.00, 05/04, page 451 of 544 The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at

Rev. 1.00, 05/04, page 452 of 544 18.11 Programmer Mode In programmer mode, the on-chip flash memory can be programmed/erased by a PROM programmer vi

Rev. 1.00, 05/04, page 453 of 544 18.12 Usage Notes The following lists notes on the use of on-board programming modes and programmer mode. 1. Perfo

Rev. 1.00, 05/04, page 454 of 544

Rev. 1.00, 05/04, page 455 of 544 Section 19 Clock Pulse Generator This LSI incorporates a clock pulse generator, which generates the system clock

Rev. 1.00, 05/04, page 15 of 544 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.

Rev. 1.00, 05/04, page 456 of 544 19.1 Oscillator Clock pulses can be supplied either by connecting a crystal resonator, or by providing external clo

Rev. 1.00, 05/04, page 457 of 544 19.1.2 External Clock Input Method Figure 19.4 shows a typical method of connecting an external clock signal. To l

Rev. 1.00, 05/04, page 458 of 544 Table 19.3 External Clock Input Conditions VCC =3.0 to 3.6 V Item Symbol Min Max Unit Test Conditions External clo

Rev. 1.00, 05/04, page 459 of 544 tDEXT*RES(Internal and external)EXTALSTBYVCC3.0 VVIHφNote: * The external clock output stabilization delay time (t

Rev. 1.00, 05/04, page 460 of 544 19.5 Subclock Input Circuit The subclock input circuit controls subclock input from the EXCL pin. To use the subcl

Rev. 1.00, 05/04, page 461 of 544 19.7 Clock Select Circuit The clock select circuit selects the system clock that is used in this LSI. A clock gene

Rev. 1.00, 05/04, page 462 of 544

Rev. 1.00, 05/04, page 463 of 544 Section 20 Power-Down Modes For operating modes after the reset state is cancelled, this LSI has not only the nor

Rev. 1.00, 05/04, page 464 of 544 20.1.1 Standby Control Register (SBYCR) SBYCR controls power-down modes. Bit Bit Name Initial Value R/W Descriptio

Rev. 1.00, 05/04, page 465 of 544 Table 20.1 Operating Frequency and Wait Time STS2 STS1 STS0 Wait Time 10 MHz 8 MHz 6 MHz 4 MHz Unit 0 0 0

Rev. 1.00, 05/04, page v of xxxiv Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Prod

Rev. 1.00, 05/04, page 16 of 544 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maxim

Rev. 1.00, 05/04, page 466 of 544 Bit Bit Name Initial Value R/W Description 6 LSON 0 R/W Low-Speed On Flag Specifies the operating mode to be e

Rev. 1.00, 05/04, page 467 of 544 20.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) MSTPCRH and MSTPCRL specify on-chip peripheral mod

Rev. 1.00, 05/04, page 468 of 544 20.2 Mode Transitions and LSI States Figure 20.1 shows the enabled mode transition diagram. The mode transition fr

Rev. 1.00, 05/04, page 469 of 544 Table 20.2 LSI Internal States in Each Operating Mode Function High- Speed Medium- Speed Sleep Module Stop Watch

Rev. 1.00, 05/04, page 470 of 544 20.3 Medium-Speed Mode The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends accord

Rev. 1.00, 05/04, page 471 of 544 20.4 Sleep Mode The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in

Rev. 1.00, 05/04, page 472 of 544 When the RES pin is driven low, system clock oscillation is started. At the same time as system clock oscillation s

Rev. 1.00, 05/04, page 473 of 544 20.6 Hardware Standby Mode The CPU makes a transition to hardware standby mode from any mode when the STBY pin is

Rev. 1.00, 05/04, page 474 of 544 20.7 Watch Mode The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode

Rev. 1.00, 05/04, page 475 of 544 20.8 Subsleep Mode The CPU makes a transition to subsleep mode when the SLEEP instruction is executed in subactive

Rev. 1.00, 05/04, page 17 of 544 H'0000H'0001H'0002H'0003H'0004H'0005H'0006H'0007H'0008H'0009H&apos

Rev. 1.00, 05/04, page 476 of 544 20.9 Subactive Mode The CPU makes a transition to subactive mode when the SLEEP instruction is executed in high-spe

Rev. 1.00, 05/04, page 477 of 544 20.10 Module Stop Mode Module stop mode can be individually set for each on-chip peripheral module. When the corre

Rev. 1.00, 05/04, page 478 of 544 20.12 Usage Notes 20.12.1 I/O Port Status The status of the I/O ports is retained in software standby mode. Theref

Rev. 1.00, 05/04, page 479 of 544 Section 21 List of Registers The register list gives information on the on-chip I/O register addresses, how the r

Rev. 1.00, 05/04, page 480 of 544 21.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is

Rev. 1.00, 05/04, page 481 of 544 Register Name Abbreviation Number of Bits Address Module Data Bus Width Number of Access States Bidirectional data

Rev. 1.00, 05/04, page 482 of 544 Register Name Abbreviation Number of Bits Address Module Data Bus Width Number of Access States Wakeup event inter

Rev. 1.00, 05/04, page 483 of 544 Register Name Abbreviation Number of Bits Address Module Data Bus Width Number of Access States Keyboard control r

Rev. 1.00, 05/04, page 484 of 544 Register Name Abbreviation Number of Bits Address Module Data Bus Width Number of Access States Low power control

Rev. 1.00, 05/04, page 485 of 544 Register Name Abbreviation Number of Bits Address Module Data Bus Width Number of Access States Output control reg

Rev. 1.00, 05/04, page 18 of 544 2.2.2 Advanced Mode • Address space Linear access to a maximum address space of 16 Mbytes is possible. • Extended

Rev. 1.00, 05/04, page 486 of 544 Register Name Abbreviation Number of Bits Address Module Data Bus Width Number of Access States Port 8 data direct

Rev. 1.00, 05/04, page 487 of 544 Register Name Abbreviation Number of Bits Address Module Data Bus Width Number of Access States I2C bus mode regis

Rev. 1.00, 05/04, page 488 of 544 Register Name Abbreviation Number of Bits Address Module Data Bus Width Number of Access States Input capture regi

Rev. 1.00, 05/04, page 489 of 544 21.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each lin

Rev. 1.00, 05/04, page 490 of 544 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TWR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit

Rev. 1.00, 05/04, page 491 of 544 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module WUEMRB WUEMR7 WUEMR6 WUEMR5 W

Rev. 1.00, 05/04, page 492 of 544 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ICRA ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 IC

Rev. 1.00, 05/04, page 493 of 544 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TIER ICIAE ICIBE ICICE ICIDE O

Rev. 1.00, 05/04, page 494 of 544 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PAODR PA7ODR PA6ODR PA5ODR PA4ODR PA3

Rev. 1.00, 05/04, page 495 of 544 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR_0 CMIEB CMIEA OVIE CCLR1 C

Rev. 1.00, 05/04, page 19 of 544 The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address

Rev. 1.00, 05/04, page 496 of 544 Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR_X CMIEB CMIEA OVIE CCLR1 CCLR0 CKS

Rev. 1.00, 05/04, page 497 of 544 21.3 Register States in Each Operating Mode Register Abbrevia- tion Reset High-Speed/ Medium- Speed Watch Sleep Su

Rev. 1.00, 05/04, page 498 of 544 Register Abbrevia- tion Reset High-Speed/ Medium- Speed Watch Sleep Sub- Active Sub-SleepModule Stop Software Stand

Rev. 1.00, 05/04, page 499 of 544 Register Abbrevia- tion Reset High-Speed/ Medium- Speed Watch Sleep Sub- Active Sub-SleepModule Stop Software Stand

Rev. 1.00, 05/04, page 500 of 544 Register Abbrevia- tion Reset High-Speed/ Medium- Speed Watch Sleep Sub- Active Sub-SleepModule Stop Software Stand

Rev. 1.00, 05/04, page 501 of 544 Register Abbrevia- tion Reset High-Speed/ Medium- Speed Watch Sleep Sub- Active Sub-SleepModule Stop Software Stand

Rev. 1.00, 05/04, page 502 of 544 Register Abbrevia- tion Reset High-Speed/ Medium- Speed Watch Sleep Sub- Active Sub-SleepModule Stop Software Stand

Rev. 1.00, 05/04, page 503 of 544 Register Abbrevia- tion Reset High-Speed/ Medium- Speed Watch Sleep Sub- Active Sub-SleepModule Stop Software Stand

Rev. 1.00, 05/04, page 504 of 544 Register Abbrevia- tion Reset High-Speed/ Medium- Speed Watch Sleep Sub- Active Sub-SleepModule Stop Software Stand

Rev. 1.00, 05/04, page 505 of 544 21.4 Register Select Conditions Lower Address Register Name Register Select Condition Module Name H'FE00 T

Rev. 1.00, 05/04, page 20 of 544 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a ma

Rev. 1.00, 05/04, page 506 of 544 Lower Address Register Name Register Select Condition Module Name TWR0MW H'FE20 TWR0SW H'FE21 TWR1 H&a

Rev. 1.00, 05/04, page 507 of 544 Lower Address Register Name Register Select Condition Module Name H'FE44 WUEMRB No condition INT H'FE

Rev. 1.00, 05/04, page 508 of 544 Lower Address Register Name Register Select Condition Module Name H'FEE8 ICRA H'FEE9 ICRB H'FEEA

Rev. 1.00, 05/04, page 509 of 544 Lower Address Register Name Register Select Condition Module Name OCRAH OCRS = 0 in TOCR H'FF94 OCRBH OCR

Rev. 1.00, 05/04, page 510 of 544 Lower Address Register Name Register Select Condition Module Name H'FFAA PAODR No condition PORT H'FF

Rev. 1.00, 05/04, page 511 of 544 Lower Address Register Name Register Select Condition Module Name H'FFC8 TCR_0 MSTP12 = 0 TMR_0, TMR_1 H

Rev. 1.00, 05/04, page 512 of 544 Lower Address Register Name Register Select Condition Module Name H'FFEA TCSR_1 No condition WDT_1 TCNT_1

Rev. 1.00, 05/04, page 513 of 544 Section 22 Electrical Characteristics 22.1 Absolute Maximum Ratings Table 22.1 lists the absolute maximum rating

Rev. 1.00, 05/04, page 514 of 544 22.2 DC Characteristics Table 22.2 lists the DC characteristics. Permitted output current values and bus drive char

Rev. 1.00, 05/04, page 515 of 544 Item Symbol Min. Typ. Max. Unit Test Conditions All output pins (except RESO)*5 — — 0.4 V IOL = 1.6 mA Ports 1 to 3

Rev. 1.00, 05/04, page 21 of 544 2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of r

Rev. 1.00, 05/04, page 516 of 544 Table 22.2 DC Characteristics (2) Conditions: VCC = 3.0 V to 3.6 V*5, VCCB = 3.0 V to 5.5 V, AVCC*1 = 3.0 V to 3.6

Rev. 1.00, 05/04, page 517 of 544 Item Symbol Min. Typ. Max. Unit Test Conditions 3.0 — 3.6 Operating Analog power supply voltage*1 AVCC 2.0 — 3.6 V

Rev. 1.00, 05/04, page 518 of 544 Table 22.3 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, Ta = –2

Rev. 1.00, 05/04, page 519 of 544 600 ΩThis LSIPorts 1 to 3LED Figure 22.2 LED Drive Circuit (Example) Table 22.4 Bus Drive Characteristics Condit

Rev. 1.00, 05/04, page 520 of 544 Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C Applicable Pins: PS2AC, PS2A

Rev. 1.00, 05/04, page 521 of 544 22.3.1 Clock Timing Table 22.5 shows the clock timing. The clock timing specified here covers clock (φ) output and

Rev. 1.00, 05/04, page 522 of 544 22.3.2 Control Signal Timing Table 22.6 shows the control signal timing. The only external interrupts that can ope

Rev. 1.00, 05/04, page 523 of 544 22.3.3 Timing of On-Chip Peripheral Modules Tables 22.7 to 22.10 show the on-chip peripheral module timing. The on

Rev. 1.00, 05/04, page 524 of 544 Condition 10 MHz Item Symbol Min. Max. Unit Test Conditions Transmit data delay time (synchronous) tTXD — 100 ns

Rev. 1.00, 05/04, page 525 of 544 Table 22.9 I2C Bus Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency,

Rev. 1.00, 05/04, page 22 of 544 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functio

Rev. 1.00, 05/04, page 526 of 544 Table 22.10 LPC Module Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 4 MHz to maximum operating frequenc

Rev. 1.00, 05/04, page 527 of 544 22.5 Flash Memory Characteristics Table 22.12 shows the flash memory characteristics. Table 22.12 Flash Memory Ch

Rev. 1.00, 05/04, page 528 of 544 Item Symbol Min. Typ. Max. Unit Test Conditions Wait time after SWE-bit setting*1 x 1 — — µs Wait time after ESU-

Rev. 1.00, 05/04, page 529 of 544 22.6 Usage Note The method of connecting an external capacitor is shown in figure 22.4. Connect the system power su

Rev. 1.00, 05/04, page 530 of 544 tOSC1tOSC1EXTALVCCSTBYRESφtDEXTtDEXT Figure 22.6 Oscillation Settling Timing φNMIIRQi(i = 0, 1, 2, 6, 7)tOSC2 Fig

Rev. 1.00, 05/04, page 531 of 544 22.7.2 Control Signal Timing The control signal timings are shown below. tRESWtRESSφtRESSRES Figure 22.8 Reset I

Rev. 1.00, 05/04, page 532 of 544 22.7.3 On-Chip Peripheral Module Timing The on-chip peripheral module timings are shown below. φPorts 1 to 9, and

Rev. 1.00, 05/04, page 533 of 544 φTMO0, TMO1TMOX, ExTMOX, TMOY, TMOA, TMOBtTMOD Figure 22.13 8-Bit Timer Output Timing φTMCI0, TMCI1TMIX, TMIY, Ex

Rev. 1.00, 05/04, page 534 of 544 SCK1, ExSCK1tSCKWtSCKrtSCKftScyc Figure 22.17 SCK Clock Input Timing TxD1, ExTxD1(transmit data)RxD1, ExRxD1(rece

Rev. 1.00, 05/04, page 535 of 544 1. ReceptionφKCLK/KD*KCLK/KD*tKBIStKBIHTransmission (b)tKBF2. Transmission (a)φKCLK/KD*T1T2tKBODNote: φ shown h

Rev. 1.00, 05/04, page 23 of 544 SP (ER7)Free areaStack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address

Rev. 1.00, 05/04, page 536 of 544 LCLKLAD3 to LAD0,SERIRQ, CLKRUN(Transmit signal)LAD3 to LAD0,SERIRQ, CLKRUNLFRAME(Receive signal)tTXDtRXHtRXStOFFL

Rev. 1.00, 05/04, page 537 of 544 Appendix A. I/O Port States in Each Processing State Table A.1 I/O Port States in Each Processing State Port Name

Rev. 1.00, 05/04, page 538 of 544 B. Product Codes Product Type Product Code Mark Code Package (Package Code) H8S/2111B-B HD64F2111BVB F2111BVTE10B

Rev. 1.00, 05/04, page 539 of 544 C. Package Dimensions For package dimensions, dimensions described in Renesas Semiconductor Packages Data Book have

Rev. 1.00, 05/04, page 540 of 544

Rev. 1.00, 05/04, page 541 of 544 Index 16-bit count mode... 210 16-bit free-running timer (FRT) ... 157

Rev. 1.00, 05/04, page 542 of 544 ICIX... 215 IICI ...

Rev. 1.00, 05/04, page 543 of 544 ICXR...302, 482, 491, 499, 507 IDR ...380, 481, 490, 498, 506 IER...

Rev. 1.00, 05/04, page 544 of 544 TCONRI ...203, 488, 496, 504, 512 TCONRS ...203, 488, 496, 504, 512 TCOR ...191

Renesas 16-Bit Single-Chip MicrocomputerHardware ManualH8S/2111BPublication Date: Rev.1.00, May 14, 2004Published by: Sales St

Rev. 1.00, 05/04, page 24 of 544 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an inte

Colophon 1.0Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japanhttp://www.renesas.comRenesa

H8S/2111BHardware Manual

Rev. 1.00, 05/04, page 25 of 544 Bit Bit Name Initial Value R/W Description 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared t

Rev. 1.00, 05/04, page vi of xxxiv Preface The H8S/2111B is a microcomputer (MCU) made up of the H8S/2000 CPU employing Renesas Technology's ori

Rev. 1.00, 05/04, page 26 of 544 2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) d

Rev. 1.00, 05/04, page 27 of 544 15 0MSB LSB15 0MSB LSB31 16MSB15 0LSBEn RnERn: En: Rn:RnH:RnL:MSB: LSB : General register ERGeneral register EGenera

Rev. 1.00, 05/04, page 28 of 544 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and l

Rev. 1.00, 05/04, page 29 of 544 2.6 Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as sh

Rev. 1.00, 05/04, page 30 of 544 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional

Rev. 1.00, 05/04, page 31 of 544 Table 2.3 Data Transfer Instructions Instruction Size*1 Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data betwee

Rev. 1.00, 05/04, page 32 of 544 Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM →

Rev. 1.00, 05/04, page 33 of 544 Table 2.4 Arithmetic Operations Instructions (2) Instruction Size*1 Function DIVXS B/W Rd ÷ Rs → Rd Performs signe

Rev. 1.00, 05/04, page 34 of 544 Table 2.5 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs

Rev. 1.00, 05/04, page 35 of 544 Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → (<bit-No.> of <EAd>)

Rev. 1.00, 05/04, page vii of xxxiv Rules: Register name: The following notation is used for cases when the same or a similar function, e.g. serial

Rev. 1.00, 05/04, page 36 of 544 Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ (<bit-No.> of <EAd>)

Rev. 1.00, 05/04, page 37 of 544 Table 2.8 Branch Instructions Instruction Size Function Branches to a specified address if a specified condition i

Rev. 1.00, 05/04, page 38 of 544 Table 2.9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handlin

Rev. 1.00, 05/04, page 39 of 544 2.6.2 Basic Instruction Formats The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction cons

Rev. 1.00, 05/04, page 40 of 544 2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed

Rev. 1.00, 05/04, page 41 of 544 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in

Rev. 1.00, 05/04, page 42 of 544 2.7.6 Immediate—#xx:8, #xx:16, or #xx:32 The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data cont

Rev. 1.00, 05/04, page 43 of 544 2.7.8 Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an

Rev. 1.00, 05/04, page 44 of 544 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing m

Rev. 1.00, 05/04, page 45 of 544 Table 2.13 Effective Address Calculation (2) No5op3123310Don't careabs@aa:87H'FFFFop3123310Don't car

Rev. 1.00, 05/04, page viii of xxxiv

Rev. 1.00, 05/04, page 46 of 544 2.8 Processing States The H8S/2000 CPU has four main processing states: the reset state, exception handling state, p

Rev. 1.00, 05/04, page 47 of 544 Program executionstateSleep modeException-handling stateSoftware standby modeRES = highReset state*1STBY = high, RES

Rev. 1.00, 05/04, page 48 of 544 2.9 Usage Notes 2.9.1 Note on TAS Instruction Usage When using the TAS instruction, use registers ER0, ER1, ER4 and

Rev. 1.00, 05/04, page 49 of 544 2.9.4 EEPMOV Instruction 1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by

Rev. 1.00, 05/04, page 50 of 544

Rev. 1.00, 05/04, page 51 of 544 Section 3 MCU Operating Modes 3.1 MCU Operating Mode Selection This LSI has two operating modes (modes 2 and 3).

Rev. 1.00, 05/04, page 52 of 544 3.2 Register Descriptions The following registers are related to the operating mode. Mode control register (MDCR) Sy

Rev. 1.00, 05/04, page 53 of 544 3.2.2 System Control Register (SYSCR) SYSCR selects a system pin function, monitors a reset source, selects the int

Rev. 1.00, 05/04, page 54 of 544 Bit Bit Name Initial Value R/W Description 1 HIE 0 R/W Host Interface Enable Controls CPU access to the keyboar

Rev. 1.00, 05/04, page 55 of 544 3.2.3 Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip

Rev. 1.00, 05/04, page ix of xxxiv Contents Section 1 Overview...

Rev. 1.00, 05/04, page 56 of 544 Bit Bit NameInitial Value R/W Description 3 FLSHE 0 R/W Flash Memory Control Register Enable Enables or disable

Rev. 1.00, 05/04, page 57 of 544 3.4 Address Map Figures 3.1 and 3.2 show the address map in each operating mode. Mode 2 (EXPE = 0)Advanced modeSingl

Rev. 1.00, 05/04, page 58 of 544 Mode 2 (EXPE = 0)Advanced modeSingle-chip modeOn-chip ROMInternal I/Oregisters 2On-chip RAMInternal I/Oregisters 1On

Rev. 1.00, 05/04, page 59 of 544 Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling

Rev. 1.00, 05/04, page 60 of 544 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sou

Rev. 1.00, 05/04, page 61 of 544 4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI e

Rev. 1.00, 05/04, page 62 of 544 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initial

Rev. 1.00, 05/04, page 63 of 544 4.4 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interr

Rev. 1.00, 05/04, page 64 of 544 4.6 Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception

Rev. 1.00, 05/04, page 65 of 544 4.7 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The sta