Renesas PROM Programming Adapters PCA7438F-64A Dokumentacja Pobierz pdf (Strona 15)

Rev.2.40 Jun 14, 2004 page 15 of 56

38C1 Group

Fig. 12 Port block diagram (1)

(

2

)

P

o

r

t

P

2

Segment output enable bit

P

u

l

l

-

d

o

w

n

c

o

n

t

r

o

l

S

e

g

m

e

n

t

o

u

t

p

u

t

e

n

a

b

l

e

b

i

t

Data bus

Port latch

V

L2

/V

L3

V

L1

/V

SS

(

1

)

P

o

r

t

P

0

D

a

t

a

b

u

s

V

L

2

/

V

L

3

V

L1

/V

SS

(

3

)

P

o

r

t

P

3

0

–

P

3

4

,

P

5

0

,

P

5

1

Key input (key-on wakeup) interrupt input

INT

0

, INT

1

interrupt input

D

a

t

a

b

u

s

Port latch

P

u

l

l

-

u

p

c

o

n

t

r

o

l

(

4

)

P

o

r

t

P

4

A

n

a

l

o

g

i

n

p

u

t

p

i

n

s

e

l

e

c

t

i

o

n

b

i

t

A

/

D

c

o

n

v

e

r

s

i

o

n

i

n

p

u

t

Data bus

Port latch

Pull-up control

(

5

)

P

o

r

t

P

5

2

P

o

r

t

l

a

t

c

h

D

a

t

a

b

u

s

Timer output

CNTR

0

interrupt input

P

u

l

l

-

u

p

c

o

n

t

r

o

l

T

i

m

e

r

X

o

p

e

r

a

t

i

o

n

m

o

d

e

b

i

t

(

P

u

l

s

e

o

u

t

p

u

t

m

o

d

e

s

e

l

e

c

t

e

d

)

(

6

)

P

o

r

t

P

5

3

Data bus

Direction

register

P

o

r

t

l

a

t

c

h

P

u

l

l

-

u

p

c

o

n

t

r

o

l

CNTR

1

interrupt input

P

u

l

l

-

d

o

w

n

c

o

n

t

r

o

l

S

e

g

m

e

n

t

o

u

t

p

u

t

e

n

a

b

l

e

b

i

t

D

i

r

e

c

t

i

o

n

r

e

g

i

s

t

e

r

D

i

r

e

c

t

i

o

n

r

e

g

i

s

t

e

r

Direction

register

Direction

register

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 58 59

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