Renesas R8C/25 Instrukcja Obsługi Pobierz pdf (Strona 4)

Rev. 1.1

R8C25 QuickDesign Guide.doc Page 4 of 10 12/23/2007

control the Reset line. The Debugging section of this document provides

additional information

3.4. MCU States after Hardware Reset

The state of each peripheral after Reset is given in the applicable sections of the

HW manual. The Reset condition of each register is also given above the register

description. Section 4 of the HW manual , Special Function Registers, provides a

single table with all the peripheral register states after Reset.

A few key Reset conditions are listed below

• All GPIO are configured as inputs (High Impedance)

• The internal low-speed oscillator (fOCO-S) is the only clock

running

• The CPU clock divider is set for divide by 8 (the CPU core is

running at approximately 125 kHz/8)

• Watchdog Timer (WDT) is not running unless the automatic start

feature is selected (see WDT section )

• App Brief on setting WDT

4. Voltage Detect

The R8C/25 has a three level voltage detection circuit which can be used for

generating Interrupts or Reset signals. The voltage levels are fixed. The three

setpoints and nominal trip points are listed below. The electrical characteristic

section of the HW manual should be referenced for specific trip setpoints and

conditions (Table 20.6 – 20.8)

Detection Level Nominal Trip Voltage Setpoint Action

Vdet0 2.3V±0.1 Reset

Vdet1 2.85 ±0.15V Reset or Interrupt

Vdet2 3.6 ±0.3V Reset or Interrupt

5. General Purpose I/O Circuit

The GPIO section of the HW manual describes exact pin configurations based on

peripheral selection and other register settings. Some general information is listed

below.

5.1. Setting Up and Using the GPIO

• Select a pin as an output by writing a “1” to the corresponding Data Direction

• The Data Direction Register (DDR) is read/write. Setting the value to a 1

selects the pin as an output. Default state for GPIO is “0” (input)

• The Data Register for ports are read/write. When the Data Register is read

with the port selected as an output the state of the output data latch (not the

pin level) is read. When the port is configured as an input the pin level is read

• GPIO require CMOS level inputs (High ≥0.8 * Vcc, Low≤ 0.2*Vcc) see

electrical characteristics for more information

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