Renesas PROM Programming Adapter PCA7408 Instrukcja Użytkownika Strona 78
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M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Rev.1.00 Oct 01, 2002 page 78 of 110
REJ03B0134-0100Z
10. ABSOLUTE MAXIMUM RATINGS
11. RECOMMENDED OPERATING CONDITIONS
(Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Power source voltage VCC
Input voltage CNVSS
Input voltage P00–P07,P10–P17, P20–P27,
P30–P34, OSC1, XIN, HSYNC,
VSYNC, RESET
Output voltage P00–P07, P10–P17, P20–P27,
P30–P32, R, G, B, OUT1, D-A,
XOUT, OSC2
Circuit current R, G, B, OUT1, P10–P17,
P20–P27, P30, P31, D-A
Circuit current R, G, B, OUT1, P00–P07, P10,
P15–P17, P20–P23, P30–P32,
D-A
Circuit current P11–P14
Circuit current P24–P27
Power dissipation
Operating temperature
Storage temperature
Symbol
VCC
VI
VI
VO
IOH
IOL1
IOL2
IOL3
Pd
Topr
Tstg
Conditions
All voltages are based
on VSS.
Output transistors are
cut off.
Ta = 25 °C
Ratings
–0.3 to 6
–0.3 to 6
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
0 to 1 (Note 1)
0 to 2 (Note 2)
0 to 6 (Note 2)
0 to 10 (Note 3)
550
–10 to 70
–40 to 125
Unit
V
V
V
V
mA
mA
mA
mA
mW
°C
°C
Parameter
V
V
V
V
V
V
V
mA
mA
mA
mA
MHz
MHz
kHz
MHz
kHz
Max.
5.5
0
VCC
VCC
0.4 VCC
0.3 VCC
0.2 VCC
1
2
6
10
8.1
8.0
100
1
400
Power source voltage (Note 4), During CPU, CRT operation
Power source voltage
“H” input voltage P00–P07,P10–P17, P20–P27, P30–P34,
SIN, SCLK, HSYNC, VSYNC, RESET, XIN,
OSC1, TIM2, TIM3, INT1, INT2, INT3
“H” input voltage SCL1, SCL2, SDA1, SDA2
(When using I
2
C-BUS)
“L” input voltage P00–P07,P10–P17, P20–P27, P30–P34
“L” input voltage SCL1, SCL2, SDA1, SDA2
(When using I
2
C-BUS)
“L” input voltage HSYNC, VSYNC, RESET,TIM2, TIM3, INT1,
INT2, INT3, XIN, OSC1, SIN, SCLK
“H” average output current (Note 1) R, G, B, OUT1, D-A, P10–P17, P20–P27,
P30, P31
“L” average output current (Note 2) R, G, B, OUT1, D-A, P00–P07, P10,
P15–P17, P20–P27, P30–P32
“L” average output current (Note 2) P11–P14
“L” average output current (Note 3) P24–P27
Oscillation frequency (for CPU operation) (Note 5) XIN
Oscillation frequency (for CRT display) (Note 5) OSC1
Input frequency TIM2, TIM3
Input frequency SCLK
Input frequency SCL1, SCL2
VCC
VSS
VIH1
VIH2
VIL1
VIL2
VIL3
IOH
IOL1
IOL2
IOL3
fCPU
fCRT
fhs1
fhs2
fhs3
Min.
4.5
0
0.8VCC
0.7VCC
0
0
0
7.9
5.0
Typ.
5.0
0
8.0
Limits
Symbol Parameter
Unit
Notes 1: The total current that flows out of the IC must be 20 mA (max.).
2: The total input current to IC (IOL1 + IOL2) must be 30 mA or less.
3: The total average input current for ports P24–P27 to IC must be 20 mA or less.
4: Connect 0.1 µ F or more capacitor externally across the power source pins VCC–VSS so as to reduce power source noise. Also
connect 0.1 µ F or more capacitor externally across the pins VCC–CNVSS.
5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit.
- 1. DESCRIPTION 0
- 2. FEATURES 0
- 3. APPLICATION 0
- REJ03B0134-0100Z 1
- Address 00E016 2
- Addresses 00DE16 and 00DF16 2
- Addresses 00E116 and 00E216 3
- Address 00E416 3
- Addresses 00E616 to 00E916 4
- Address 00E516 4
- Address 00EA16 5
- Addresses 00EC16 5
- Address 00ED16 6
- Addresses 00EE16 6
- Address 00EF16 7
- Addresses 00F416 7
- Address 00F516 8
- Addresses 00F916 8
- Address 00FB16 9
- Addresses 00FC16 9
- Address 00FD16 10
- Addresses 00FE16 10
- Address 00FF16 11
- Addresses 021B16 11
- 42P2R-A/E 13
- REVISION HISTORY 14
- RENESAS SALES OFFICES 15
- 8. FUNCTION BLOCK DESCRIPTION 16
- 8.1.1 CPU Mode Register 16
- RCR1 RCR0 21
- TABLE OF CONTENTS 24
- (4) Serial I/O interrupt 25
- (5) f(XIN)/4096 interrupt 25
- (6) Multi-master I 25
- C-BUS interface interrupt 25
- (7) BRK instruction interrupt 25
- 8.4 TIMERS 29
- 8.4.1 Timer 1 29
- 8.4.2 Timer 2 29
- 8.4.3 Timer 3 29
- 8.4.4 Timer 4 29
- Timer 34 Mode Register 30
- 8.5 SERIAL I/O 32
- 16), and the transfer 33
- OUT pin. Transfer 33
- 4. PIN CONFIGURATION 35
- Outline 42P4B 35
- Outline 42P2R-A/E 35
- 8.6 MULTI-MASTER I 37
- C-BUS INTERFACE 37
- C Data Shift Register 38
- C Address Register 39
- 16) is used to set ACK 40
- C Control Register 42
- (1) 7-bit addressing format 47
- (2) 10-bit addressing format 47
- (5) Writing to I 50
- C status register 50
- 8.8 A-D COMPARATOR 56
- 5. FUNCTIONAL BLOCK DIAGRAM 57
- 8.9 D-A CONVERTER 59
- 8.10 ROM CORRECTION FUNCTION 61
- 8.11 OSD FUNCTIONS 62
- OSD Control Register 65
- 8.11.1 Display Position 66
- 6. PERFORMANCE OVERVIEW 68
- Vertical Position Register i 69
- Horizontal Position Register 70
- 8.11.2 Character Size 71
- 8.11.3 Clock for OSD 73
- 8.11.4 Memory for OSD 74
- Border Selection Register 80
- 8.11.7 Multiline Display 81
- 8.11.8 OSD Output Pin Control 82
- 8.13. RESET CIRCUIT 85
- 8.14 CLOCK GENERATING CIRCUIT 86
- 8.17 ADDRESSING MODE 87
- 8.18 MACHINE INSTRUCTIONS 87
- 9. TECHNICAL NOTES 87
- 8.16 AUTO-CLEAR CIRCUIT 87
- 10. ABSOLUTE MAXIMUM RATINGS 88
- 7. PIN DESCRIPTION 90
- + Power source voltage 91
- 15. MULTI-MASTER I 92
- 16. PROM PROGRAMMING METHOD 93
- M37221EASP 95
- M37221EAFP 95
- 19. APPENDIX 96
- Pin Configuration (TOP VIEW) 96
- Memory Map 98
- Register (SFR) 100
- Program Counter at Reset 104
- Structure of Register 105
- Address 00C716 106
- Address 00CB16 107
- Address 00CD16 107
- Address 00D516 108
- Address 00D616 108
- Address 00D816 109
- Address 00D716 109
- Address 00D916 110
- Address 00DA16 110
- Address 00DB16 111
- Address 00DC16 111
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