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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
22
Fig. 16 Interrupt control
Fig. 17 Structure of interrupt-related registers
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2
CNTR
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CNTR
1
interrupt request bit
Timer 1 interrupt request bit
INT
2
interrupt request bit
INT
3
interrupt request bit
Key input interrupt request bit
ADT/AD conversion interrupt request bit
Not used (returns 0 when read)
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Notes on interrupts
When setting the followings, the interrupt request bit may be set to
1.
When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A
16)
Timer X mode register (address 27
16)
Timer Y mode register (address 28
16)
When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: A-D control regsiter (address 34
16)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to 0 (disabled).
Set the interrupt edge select bit or the interrupt source select bit
to 1.
Set the corresponding interrupt request bit to 0 after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to 1 (enabled).
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