Renesas SuperH SH7710 E10A Instrukcja Użytkownika Pobierz pdf (Strona 6)

■ SuperH Architecture:

Common Features

RISC-type instruction set

• Instruction length: fixed

16-bit-long instructions for

improved code efficiency

• Load-store architecture

(basic arithmetic and logic

operations are carried out

between registers)

• Delayed unconditional branch

instructions reduce pipeline

disruption

• Instruction set optimized for

the C language

4

SuperH

®

Family of Microcontrollers & Microprocessors

R0

31 0

31 0

R1

R0

31 0

31

0

R1

R2

R7

R2

SR: Status Register

GBR: Global Base Register

General Register

Control Register

System Register

Program Counter

R14

R15

R7

MD RR RI M Q I I I I . . S T

31 0

31 0

MACH: Multiply and Accumulator High

MACL: Multiply and Accumulator Low

: Accessible only in Privilege mode (SH-3 and SH-4 only)

PR: Procedure Register

PC: Program Counter

•

•

•

•

•

•

-

-

-

-

-

-

•

•

•

SSR: Saved Status Register

31

0

SPC: Saved Program Counter

VBR: Vector Base Register

Code

compatibility

Code

compatibility

SH-4A

103 instructions

FPU, Cache operations

SH-4

91 instructions

Single/double-precision FPU

SH-3

68 instructions

MMU Control

SH-2

62 instructions

32-bit MAC

SH-1

56 instructions

SH3-DSP

160 instructions

92 DSP instructions

SH2-DSP

154 instructions

92 DSP instructions

Code

compatibility

SH-2A

91 instructions

Enhanced shift, bit,

& divide operations

112 Instructions

with FPU

Mixed

16-/32-bit length

Fixed

16-bit length

Mixed

16-/32-bit length

SuperH Instruction Set

SuperH Programming Model

CPU register set

• Sixteen 32-bit general-purpose

registers

• Up to 7 control registers and

4 system registers for fast jumps

and interrupt response

Efficient caching scheme

for each series

• LRU replacement policy

algorithm for improved hit rates

• Each family’s cache architecture

has been optimized for the best

latency/miss-rate balance:

e.g., SH-4A devices have

32KB + 32KB, 4-way

set-associative, separate

instruction and operand caches

for improved performance

1 2 3 4 5 6 7 8 9 10 11 ... 41 42

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