Renesas M16C/30P Instrukcja Użytkownika Pobierz pdf (Strona 49)

M16C/30P Group 5. Electrical Characteristics

Rev.1.22 Mar 30, 2007 Page 47 of 53

REJ03B0088-0122

VCC1=VCC2=3V

Switching Characteristics

CC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)

NOTES:

1. Calculated according to the BCLK frequency as follows:

n is “1” for 1-wait setting, f(BCLK) is 12.5MHz or less.

2. Calculated according to the BCLK frequency as follows:

3. This standard value shows the timing when the output is off, and

does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

Hold time of data bus is expressed in

t = −CR X ln (1−V

OL / VCC1)

by a circuit of the right figure.

For example, when V

OL = 0.2VCC1, C = 30pF, R = 1kΩ, hold time

of output ”L” level is

t = −30pF X 1kΩ X In(1−0.2V

CC1 / VCC1)

= 6.7ns.

Table 5.44 Memory Expansion and Microprocessor Modes (for 1 wait setting and external area

access)

Symbol Parameter

Standard

Unit

Min. Max.

d(BCLK-AD) Address Output Delay Time

See

Figure 5.8

30 ns

h(BCLK-AD) Address Output Hold Time (in relation to BCLK) 0 ns

h(RD-AD) Address Output Hold Time (in relation to RD) 0 ns

h(WR-AD) Address Output Hold Time (in relation to WR) (NOTE 2) ns

d(BCLK-CS) Chip Select Output Delay Time 30 ns

h(BCLK-CS) Chip Select Output Hold Time (in relation to BCLK) 0 ns

d(BCLK-ALE) ALE Signal Output Delay Time 25 ns

h(BCLK-ALE) ALE Signal Output Hold Time -4 ns

d(BCLK-RD) RD Signal Output Delay Time 30 ns

h(BCLK-RD) RD Signal Output Hold Time 0 ns

d(BCLK-WR) WR Signal Output Delay Time 30 ns

h(BCLK-WR) WR Signal Output Hold Time 0 ns

d(BCLK-DB) Data Output Delay Time (in relation to BCLK) 40 ns

h(BCLK-DB) Data Output Hold Time (in relation to BCLK)

(3)

4ns

d(DB-WR) Data Output Delay Time (in relation to WR) (NOTE 1) ns

th(WR-DB) Data Output Hold Time (in relation to WR)

(3)

(NOTE 2) ns

d(BCLK-HLDA) HLDA Output Delay Time 40 ns

n0.5–()x10

fBCLK()

------------------------------------ 40 n s[]–

0.5x10

fBCLK()

------------------------10ns[]–

DBi

1 2 ... 44 45 46 47 48 49 50 51 52 53 54 ... 58 59

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