Renesas SH7781 Instrukcja Użytkownika

Revision Date: Jan. 10, 200832 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC Engine Family SH7780 Series R

Rev.1.00 Jan. 10, 2008 Page x of xxx REJ09B0261-0100 5.2.2 Exception Event Register (EXPEVT)...

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 70 of 1658 REJ09B0261-0100 I1 I2 I3 ID s1 s2 s3 WBI3I3I3I3I3I3I3I1 I2 ID s1 s2 s3WBI1 I2 ID s1 s2 s3WBI

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 970 of 1658 REJ09B0261-0100 Figure 20.1 shows the GDTA block diagram

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 971 of 1658 REJ09B0261-0100 (1) Target Interface The target interfa

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 972 of 1658 REJ09B0261-0100 (6) Buffer RAM Buffer RAM consists of t

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 973 of 1658 REJ09B0261-0100 20.2 GDTA Address Space Figure 20.2 sho

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 974 of 1658 REJ09B0261-0100 20.3 Register Descriptions Table 20.1 t

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 975 of 1658 REJ09B0261-0100 Table 20.2 GDTA Register Configuration

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 976 of 1658 REJ09B0261-0100 Table 20.3 GDTA Register Configuration

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 977 of 1658 REJ09B0261-0100 Table 20.4 GDTA Register States in Each

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 978 of 1658 REJ09B0261-0100 Table 20.6 GDTA States in Each Processi

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 979 of 1658 REJ09B0261-0100 20.3.1 GA Mask Register (GACMR) GACMR i

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 71 of 1658 REJ09B0261-0100 I1 I2 I3 ID s1 s2 s3 WBI3I3I3I3I3I3I3I1 I2 IDWBI1 I2 ID S1 S2 S3E1s1 E2s2 E3

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 980 of 1658 REJ09B0261-0100 20.3.2 GA Enable Register (GACER) GACER

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 981 of 1658 REJ09B0261-0100 20.3.3 GA Interrupt Source Indicating R

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 982 of 1658 REJ09B0261-0100 20.3.4 GA Interrupt Source Indication C

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 983 of 1658 REJ09B0261-0100 20.3.5 GA Interrupt Enable Register (GA

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 984 of 1658 REJ09B0261-0100 20.3.6 GA CL Input Data Alignment Regis

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 985 of 1658 REJ09B0261-0100 20.3.7 GA CL Output Data Alignment Regi

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 986 of 1658 REJ09B0261-0100 20.3.8 GA MC Input Data Alignment Regis

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 987 of 1658 REJ09B0261-0100 20.3.9 GA MC Output Data Alignment Regi

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 988 of 1658 REJ09B0261-0100 20.3.10 GA Buffer RAM 0 Data Alignment

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 989 of 1658 REJ09B0261-0100 20.3.11 GA Buffer RAM 1 Data Alignment

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 72 of 1658 REJ09B0261-0100 I1 I2 I3 ID s1 s2 s3 WBMSI3I3I3I3I3I3I3I3I1 I2 ID E1 M2 M3E1 M2 M3MSE1 M2 M3

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 990 of 1658 REJ09B0261-0100 20.3.12 CL Command FIFO (CLCF) CLCF is

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 991 of 1658 REJ09B0261-0100 2. Setting Method When Setting Values

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 992 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descript

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 993 of 1658 REJ09B0261-0100 20.3.14 CL Status Register (CLSR) CLSR

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 994 of 1658 REJ09B0261-0100 20.3.15 CL Frame Width Setting Register

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 995 of 1658 REJ09B0261-0100 20.3.16 CL Frame Height Setting Registe

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 996 of 1658 REJ09B0261-0100 20.3.17 CL Input Y Padding Size Setting

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 997 of 1658 REJ09B0261-0100 20.3.18 CL Input UV Padding Size Settin

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 998 of 1658 REJ09B0261-0100 20.3.19 CL Output Padding Size Setting

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 999 of 1658 REJ09B0261-0100 20.3.20 CL Palette Pointer Register (CL

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 73 of 1658 REJ09B0261-0100 I1 I2 I3 ID s1 s2 s3s1 s2 s3 WBs1 s2 s3 WBFS1 FS2 FS3 FS4FS1 FS2 FS3 FS4FSFS

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1000 of 1658 REJ09B0261-0100 20.3.21 MC Command FIFO (MCCF) MCCF is

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1001 of 1658 REJ09B0261-0100 Writing Order Intra Macroblock Processi

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1002 of 1658 REJ09B0261-0100 ⎯ Bit 26: Indicates whether or not the

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1003 of 1658 REJ09B0261-0100 20.3.22 MC Status Register (MCSR) MCSR

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1004 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descript

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1005 of 1658 REJ09B0261-0100 20.3.24 MC Frame Height Setting Regist

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1006 of 1658 REJ09B0261-0100 20.3.25 MC Y Padding Size Setting Regi

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1007 of 1658 REJ09B0261-0100 20.3.26 MC UV Padding Size Setting Reg

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1008 of 1658 REJ09B0261-0100 20.3.27 MC Output Frame Y Pointer Regi

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1009 of 1658 REJ09B0261-0100 20.3.29 MC Output Frame V Pointer Regi

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 74 of 1658 REJ09B0261-0100 I1 I2 I3 ID s1 s2 s3FS1 FS2 FS3 FS4FSI1 I2 I3IDI1 I2 I3 ID s1 s2 s3FS1 FS2 F

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1010 of 1658 REJ09B0261-0100 20.3.31 MC Past Frame U Pointer Regist

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1011 of 1658 REJ09B0261-0100 20.3.33 MC Future Frame Y Pointer Regi

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1012 of 1658 REJ09B0261-0100 20.3.35 MC Future Frame V Pointer Regi

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1013 of 1658 REJ09B0261-0100 20.4 GDTA Operation 20.4.1 Explanatio

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1014 of 1658 REJ09B0261-0100 Table 20.7 shows YUYV4:2:2 conversion s

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1015 of 1658 REJ09B0261-0100 (2) Overview of ARGB Conversion Functi

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1016 of 1658 REJ09B0261-0100 Table 20.8 shows ARGB8888 conversion se

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1017 of 1658 REJ09B0261-0100 No. Operation Description (4) ARGB con

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1018 of 1658 REJ09B0261-0100 [Step (1) Clear the CL access mask]Afte

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1019 of 1658 REJ09B0261-0100 20.4.2 Explanation of MC Operation By

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 75 of 1658 REJ09B0261-0100 I1 I2 I3 IDFE1 FE2 FE3FEPLFEPLFE4 FE5 FE6 FSI1 I2 I3IDFE1 FE2 FE3 FE4 FE5 FE

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1020 of 1658 REJ09B0261-0100 (1) Estimated Image Generation Functio

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1021 of 1658 REJ09B0261-0100 Table 20.9 shows estimated image genera

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1022 of 1658 REJ09B0261-0100 No. Operation Description (2) Calculat

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1023 of 1658 REJ09B0261-0100 No. Operation Description (3) Calculat

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1024 of 1658 REJ09B0261-0100 No. Operation Description (3) Calculat

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1025 of 1658 REJ09B0261-0100 No. Operation Description (4) Calculat

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1026 of 1658 REJ09B0261-0100 No. Operation Description (6) Half-pix

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1027 of 1658 REJ09B0261-0100 No. Operation Description (7) IDCT dat

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1028 of 1658 REJ09B0261-0100 StartEndIs an interrupt used to recogni

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1029 of 1658 REJ09B0261-0100 20.5 Interrupt Processing In the GDTA,

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 76 of 1658 REJ09B0261-0100 4.2 Parallel-Executability Instructions are categorized into six groups acc

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1030 of 1658 REJ09B0261-0100 D0 D1 D2 D3 D4 D5 D6 D7D4 D5 D6 D7 D0 D

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1031 of 1658 REJ09B0261-0100 20.7 Usage Notes When using the GDTA,

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1032 of 1658 REJ09B0261-0100 20.7.3 Regarding Frequency Changes Dur

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1033 of 1658 REJ09B0261-0100 Section 21 Serial Communication In

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1034 of 1658 REJ09B0261-0100 • Full-duplex communication capabil

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1035 of 1658 REJ09B0261-0100 Figure 21.1 shows a block diagram of

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1036 of 1658 REJ09B0261-0100 SPTRWD7D6RQDRTSIOCSPTRRSPTRWRQDRTSDT

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1037 of 1658 REJ09B0261-0100 SPTRWD5D4RQDCTSIOCSPTRRSPTRWRQDCTSDT

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1038 of 1658 REJ09B0261-0100 SPTRWD3D2RQDSCKIOCSPTRRSPTRWRQDSCKDT

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1039 of 1658 REJ09B0261-0100 SPTRRLegend:SPTRR: Read from SCSPTRS

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 77 of 1658 REJ09B0261-0100 Instruction Group Instruction FE FADD FSUB FCMP (S/D) FCNVDS FCNVSD FDIV FIP

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1040 of 1658 REJ09B0261-0100 21.3 Register Descriptions The SCIF

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1041 of 1658 REJ09B0261-0100 Ch. Register Name Abbrev. R/W P4 A

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1042 of 1658 REJ09B0261-0100 Ch. Register Name Abbrev. R/W P4 A

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1043 of 1658 REJ09B0261-0100 Table 21.2 Register Configuration (

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1044 of 1658 REJ09B0261-0100 Ch. Register Name Abbrev. Power-on

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1045 of 1658 REJ09B0261-0100 Ch. Register Name Abbrev. Power-on

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1046 of 1658 REJ09B0261-0100 21.3.1 Receive Shift Register (SCRS

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1047 of 1658 REJ09B0261-0100 21.3.3 Transmit Shift Register (SCT

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1048 of 1658 REJ09B0261-0100 21.3.5 Serial Mode Register (SCSMR)

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1049 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descr

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 78 of 1658 REJ09B0261-0100 Table 4.3 Combination of Preceding and Following Instructions Preceding I

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1050 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descr

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1051 of 1658 REJ09B0261-0100 21.3.6 Serial Control Register (SCS

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1052 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descr

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1053 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descr

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1054 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descr

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1055 of 1658 REJ09B0261-0100 21.3.7 Serial Status Register n (SC

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1056 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descr

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1057 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descr

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1058 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descr

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1059 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descr

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 79 of 1658 REJ09B0261-0100 4.3 Issue Rates and Execution Cycles Instruction execution cycles are summa

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1060 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descr

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1061 of 1658 REJ09B0261-0100 21.3.8 Bit Rate Register n (SCBRR)

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1062 of 1658 REJ09B0261-0100 21.3.9 FIFO Control Register n (SCF

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1063 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descr

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1064 of 1658 REJ09B0261-0100 21.3.10 Transmit FIFO Data Count Re

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1065 of 1658 REJ09B0261-0100 21.3.11 Receive FIFO Data Count Reg

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1066 of 1658 REJ09B0261-0100 21.3.12 Serial Port Register n (SCS

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1067 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descr

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1068 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descr

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1069 of 1658 REJ09B0261-0100 21.3.13 Line Status Register n (SCL

Rev.1.00 Jan. 10, 2008 Page xi of xxx REJ09B0261-0100 7.1.1 Address Spaces ...

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 80 of 1658 REJ09B0261-0100 Table 4.4 Issue Rates and Execution Cycles Functional Category No. Instruct

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1070 of 1658 REJ09B0261-0100 21.3.14 Serial Error Register n (SC

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1071 of 1658 REJ09B0261-0100 21.4 Operation 21.4.1 Overview The

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1072 of 1658 REJ09B0261-0100 Clocked Synchronous Mode • Data len

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1073 of 1658 REJ09B0261-0100 Table 21.5 SCSMR and SCSCR Settings

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1074 of 1658 REJ09B0261-0100 21.4.2 Operation in Asynchronous Mo

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1075 of 1658 REJ09B0261-0100 (1) Data Transfer Format Table 21.6

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1076 of 1658 REJ09B0261-0100 (2) Clock Either an internal clock

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1077 of 1658 REJ09B0261-0100 Figure 21.8 shows a sample SCIF init

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1078 of 1658 REJ09B0261-0100 (4) Serial Data Transmission (Async

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1079 of 1658 REJ09B0261-0100 In serial transmission, the SCIF ope

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 81 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue RateExecution Cy

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1080 of 1658 REJ09B0261-0100 Figure 21.10 shows an example of the

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1081 of 1658 REJ09B0261-0100 (5) Serial Data Reception (Asynchro

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1082 of 1658 REJ09B0261-0100 Error handlingReceive error handling

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1083 of 1658 REJ09B0261-0100 In serial reception, the SCIF operat

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1084 of 1658 REJ09B0261-0100 5. When modem control is enabled, t

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1085 of 1658 REJ09B0261-0100 21.4.3 Operation in Clocked Synchro

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1086 of 1658 REJ09B0261-0100 (1) Data Transfer Format A fixed 8-

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1087 of 1658 REJ09B0261-0100 Start of initializationClear TE and

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1088 of 1658 REJ09B0261-0100 (4) Serial Data Transmission (Clock

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1089 of 1658 REJ09B0261-0100 In serial transmission, the SCIF ope

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 82 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue RateExecution Cy

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1090 of 1658 REJ09B0261-0100 (5) Serial Data Reception (Clocked

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1091 of 1658 REJ09B0261-0100 Error handlingClear ORER flag in SCL

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1092 of 1658 REJ09B0261-0100 Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1093 of 1658 REJ09B0261-0100 (6) Transmitting and Receiving Seri

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1094 of 1658 REJ09B0261-0100 21.5 SCIF Interrupt Sources and the

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1095 of 1658 REJ09B0261-0100 Table 21.7 SCIF Interrupt Sources I

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1096 of 1658 REJ09B0261-0100 21.6 Usage Notes Note the following

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1097 of 1658 REJ09B0261-0100 (4) Sending a Break Signal The inpu

21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1098 of 1658 REJ09B0261-0100 Thus, the reception margin in asynch

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1099 of 1658 REJ09B0261-0100 Section 22 Serial I/O with FIFO (SIOF) This LSI is equ

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 83 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue RateExecution Cy

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1100 of 1658 REJ09B0261-0100 Figure 22.1 shows a block diagram of the SIOF. P/STransm

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1101 of 1658 REJ09B0261-0100 22.2 Input/Output Pins Table 22.1 shows the pin configu

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1102 of 1658 REJ09B0261-0100 22.3 Register Descriptions Table 22.2 shows the registe

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1103 of 1658 REJ09B0261-0100 Table 22.3 Register States in Each Operating Mode Name

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1104 of 1658 REJ09B0261-0100 22.3.1 Mode Register (SIMDR) SIMDR is a 16-bit readable

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1105 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7 TXDIZ 0

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1106 of 1658 REJ09B0261-0100 22.3.2 Control Register (SICTR) SICTR is a 16-bit reada

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1107 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 8 RXE 0 R/W

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1108 of 1658 REJ09B0261-0100 22.3.3 Transmit Data Register (SITDR) SITDR is a 32-bit

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1109 of 1658 REJ09B0261-0100 22.3.4 Receive Data Register (SIRDR) SIRDR is a 32-bit

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 84 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue RateExecution Cy

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1110 of 1658 REJ09B0261-0100 22.3.5 Transmit Control Data Register (SITCR) SITCR is

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1111 of 1658 REJ09B0261-0100 22.3.6 Receive Control Data Register (SIRCR) SIRCR is a

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1112 of 1658 REJ09B0261-0100 22.3.7 Status Register (SISTR) SISTR is a 16-bit readab

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1113 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 12 TDREQ 0

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1114 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 9 RFFUL 0 R

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1115 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 SAERR 0 R/

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1116 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 TFOVF 0 R/

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1117 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 1 RFUDF 0 R/

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1118 of 1658 REJ09B0261-0100 22.3.8 Interrupt Enable Register (SIIER) SIIER is a 16-

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1119 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 10 RCRDYE

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 85 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue RateExecution Cy

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1120 of 1658 REJ09B0261-0100 22.3.9 FIFO Control Register (SIFCTR) SIFCTR is a 16-bi

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1121 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7 to 5 RFWM

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1122 of 1658 REJ09B0261-0100 22.3.10 Clock Select Register (SISCR) SISCR is a 16-bit

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1123 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0 BRDV

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1124 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 11 to 8 TDL

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1125 of 1658 REJ09B0261-0100 22.3.12 Receive Data Assign Register (SIRDAR) SIRDAR is

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1126 of 1658 REJ09B0261-0100 22.3.13 Control Data Assign Register (SICDAR) SICDAR is

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1127 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 to 0 CD1A

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1128 of 1658 REJ09B0261-0100 22.4 Operation 22.4.1 Serial Clocks (1) Master/Slave

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1129 of 1658 REJ09B0261-0100 Table 22.5 shows an example of serial clock frequency. T

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 86 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue RateExecution Cy

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1130 of 1658 REJ09B0261-0100 SIOF_SCKSIOF_RXDSIOF_TXDSIOF_SYNC1-bit delayStart bit da

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1131 of 1658 REJ09B0261-0100 SIOF_SCKSIOF_SYNCSIOF_TXDSIOF_RXD(a) Falling-edge sampli

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1132 of 1658 REJ09B0261-0100 (2) Frame Length The frame length to be transferred by

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1133 of 1658 REJ09B0261-0100 22.4.4 Register Allocation of Transfer Data (1) Transm

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1134 of 1658 REJ09B0261-0100 Table 22.8 Audio Mode Specification for Transmit Data B

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1135 of 1658 REJ09B0261-0100 The number of channels in control data is specified by t

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1136 of 1658 REJ09B0261-0100 (2) Control by Secondary FS (Slave Mode 2) The CODEC no

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1137 of 1658 REJ09B0261-0100 22.4.6 FIFO (1) Overview The transmit and receive FIFO

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1138 of 1658 REJ09B0261-0100 Table 22.12 Conditions to Issue Receive Request RFWM2 t

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1139 of 1658 REJ09B0261-0100 22.4.7 Transmit and Receive Procedures Set each registe

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 87 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue RateExecution Cy

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1140 of 1658 REJ09B0261-0100 (2) Reception in Master Mode Figure 22.10 shows an exam

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1141 of 1658 REJ09B0261-0100 (3) Transmission in Slave Mode Figure 22.11 shows an ex

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1142 of 1658 REJ09B0261-0100 (4) Reception in Slave Mode Figure 22.12 shows an examp

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1143 of 1658 REJ09B0261-0100 (5) Transmit/Receive Reset The SIOF can separately rese

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1144 of 1658 REJ09B0261-0100 22.4.8 Interrupts The SIOF has one type of interrupt. (

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1145 of 1658 REJ09B0261-0100 (2) Regarding Transmit and Receive Classification The t

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1146 of 1658 REJ09B0261-0100 22.4.9 Transmit and Receive Timing Figures 22.13 to 22.

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1147 of 1658 REJ09B0261-0100 (2) 8-bit Monaural Data (2) Synchronous pulse method, f

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1148 of 1658 REJ09B0261-0100 (4) 16-bit Stereo Data (1) L/R method, rising edge samp

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1149 of 1658 REJ09B0261-0100 (6) 16-bit Stereo Data (3) Synchronous pulse method, fa

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 88 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue RateExecution Cy

22. Serial I/O with FIFO (SIOF) Rev.1.00 Jan. 10, 2008 Page 1150 of 1658 REJ09B0261-0100 (8) Synchronization-Pulse Output Mode at End of Each Sl

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1151 of 1658 REJ09B0261-0100 Section 23 Serial Peripheral Interface (HSPI) T

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1152 of 1658 REJ09B0261-0100 Figure 23.1 is a block diagram of the HSPI. HSPI_

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1153 of 1658 REJ09B0261-0100 23.2 Input/Output Pins The input/output pins of

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1154 of 1658 REJ09B0261-0100 Table 23.3 Register Configuration (2) Register N

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1155 of 1658 REJ09B0261-0100 23.3.1 Control Register (SPCR) SPCR is a 32-bit

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1156 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 IDI

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1157 of 1658 REJ09B0261-0100 The serial clock frequency can be computed using

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1158 of 1658 REJ09B0261-0100 23.3.2 Status Register (SPSR) SPSR is a 32-bit r

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1159 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 8 TX

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 89 of 1658 REJ09B0261-0100 Section 5 Exception Handling 5.1 Summary of Exception Handling Ex

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1160 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 RXO

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1161 of 1658 REJ09B0261-0100 23.3.3 System Control Register (SPSCR) SPSCR is

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1162 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 8 FF

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1163 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 RX

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1164 of 1658 REJ09B0261-0100 23.3.5 Receive Buffer Register (SPRBR) SPRBR is

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1165 of 1658 REJ09B0261-0100 23.4 Operation 23.4.1 Operation Overview with F

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1166 of 1658 REJ09B0261-0100 The HSPI_CS pin should be used to select the HSPI

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1167 of 1658 REJ09B0261-0100 23.4.3 Timing Diagrams The following diagrams ex

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1168 of 1658 REJ09B0261-0100 Data transfer cycleHSPI_CLK (CLKP = 0)HSPI_CLK

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1169 of 1658 REJ09B0261-0100 23.4.4 HSPI Software Reset If any of the control

Rev.1.00 Jan. 10, 2008 Page xii of xxx REJ09B0261-0100 7.8.1 Overview of 32-Bit Address Extended Mode...

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 90 of 1658 REJ09B0261-0100 Table 5.2 States of Register in Each Operating Mode Register Name

23. Serial Peripheral Interface (HSPI) Rev.1.00 Jan. 10, 2008 Page 1170 of 1658 REJ09B0261-0100 23.4.7 Flags and Interrupt Timing The interrupt

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1171 of 1658 REJ09B0261-0100 Section 24 Multimedia Card Interface (MMCIF) Thi

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1172 of 1658 REJ09B0261-0100 Figure 24.1 shows a block diagram of the MMCIF. MM

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1173 of 1658 REJ09B0261-0100 24.3 Register Descriptions Table 24.2 shows the M

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1174 of 1658 REJ09B0261-0100 Register Name Abbrev. R/W P4 Address Area 7 Ad

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1175 of 1658 REJ09B0261-0100 Table 24.3 Register Configuration (2) Register Na

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1176 of 1658 REJ09B0261-0100 Register Name Abbrev. Power-on Reset by PRESET Pi

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1177 of 1658 REJ09B0261-0100 24.3.1 Command Registers 0 to 5 (CMDR0 to CMDR5)

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1178 of 1658 REJ09B0261-0100 (2) CMDR5 Bit: Initial value:R/W:7654321000000000

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1179 of 1658 REJ09B0261-0100 Bit: Initial value:R/W:7654321000000000RCMDSTARTRR

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 91 of 1658 REJ09B0261-0100 5.2.2 Exception Event Register (EXPEVT) The exception event registe

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1180 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 — 0

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1181 of 1658 REJ09B0261-0100 In write data transmission, the contents of the co

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1182 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 FIFO_

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1183 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 0 REQ 0

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1184 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 4 DTI

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1185 of 1658 REJ09B0261-0100 (2) INTCR1 Bit: Initial value:R/W:7654321000000 0

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1186 of 1658 REJ09B0261-0100 (3) INTCR2 Bit: Initial value:R/W:7654321000000 0

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1187 of 1658 REJ09B0261-0100 24.3.6 Interrupt Status Registers 0 to 2 (INTSTR0

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1188 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description Interr

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1189 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description Interr

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 92 of 1658 REJ09B0261-0100 5.2.3 Interrupt Event Register (INTEVT) The interrupt event registe

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1190 of 1658 REJ09B0261-0100 (2) INTSTR1 Bit: Initial value:R/W:7654321000000

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1191 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description Interr

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1192 of 1658 REJ09B0261-0100 (3) INTSTR2 Bit: Initial value:R/W:7654321000000

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1193 of 1658 REJ09B0261-0100 24.3.7 Transfer Clock Control Register (CLKON) CL

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1194 of 1658 REJ09B0261-0100 24.3.8 Command Timeout Control Register (CTOCR) C

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1195 of 1658 REJ09B0261-0100 24.3.9 Transfer Byte Number Count Register (TBCR)

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1196 of 1658 REJ09B0261-0100 24.3.10 Mode Register (MODER) MODER is an 8-bit r

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1197 of 1658 REJ09B0261-0100 24.3.11 Command Type Register (CMDTYR) CMDTYR is

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1198 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 TY3

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1199 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 RTY

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 93 of 1658 REJ09B0261-0100 5.2.4 Non-Support Detection Exception Register (EXPMASK) The non-su

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1200 of 1658 REJ09B0261-0100 Table 24.5 summarizes the correspondence between t

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1201 of 1658 REJ09B0261-0100 CMD CMDTYR RSPTYR INDEX Abbreviation resp 6

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1202 of 1658 REJ09B0261-0100 24.3.13 Transfer Block Number Counter (TBNCR) A v

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1203 of 1658 REJ09B0261-0100 24.3.14 Response Registers 0 to 16, D (RSPR0 to R

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1204 of 1658 REJ09B0261-0100 (1) RSPR0 to RSPR16 Bit: Initial value:R/W:765432

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1205 of 1658 REJ09B0261-0100 24.3.15 Data Timeout Register (DTOUTR) DTOUTR spe

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1206 of 1658 REJ09B0261-0100 24.3.16 Data Register (DR) DR is a register for r

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1207 of 1658 REJ09B0261-0100 H'011 word (2 bytes)64 wordsH'23H'4

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1208 of 1658 REJ09B0261-0100 24.3.18 DMA Control Register (DMACR) DMACR sets D

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1209 of 1658 REJ09B0261-0100 24.4 Operation The multimedia card is an external

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 94 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 5 ⎯ All 0 R Reser

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1210 of 1658 REJ09B0261-0100 (1) Operation of Broadcast Commands CMD0, CMD1, C

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1211 of 1658 REJ09B0261-0100 (3) Operation of Commands Not Requiring Command R

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1212 of 1658 REJ09B0261-0100 Ye sStart of command sequenceSet command data in C

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1213 of 1658 REJ09B0261-0100 • The command response is received from the card.

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1214 of 1658 REJ09B0261-0100 MMCCLKMMCCMDMMCDATCMDSTRT(CMDSTART)INTSTR0(CMDI)CS

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1215 of 1658 REJ09B0261-0100 Start of command sequenceSet command data in CMDR

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1216 of 1658 REJ09B0261-0100 (5) Commands with Read Data Flash memory operatio

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1217 of 1658 REJ09B0261-0100 • The end of the command sequence is detected by

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1218 of 1658 REJ09B0261-0100 MMCCLKMMCCMDMMCDATCMDSTRT(CMDSTART)INTSTR0(CMDI)(C

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1219 of 1658 REJ09B0261-0100 MMCCLKMMCCMDMMCDATCMDSTRT(CMDSTART)INTSTR0(CMDI)(C

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 95 of 1658 REJ09B0261-0100 5.3 Exception Handling Functions 5.3.1 Exception Handling Flow In

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1220 of 1658 REJ09B0261-0100 CMD11 (READ_DAT_UNTIL_STOP)CMD12 (STOP_TRANSMISSIO

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1221 of 1658 REJ09B0261-0100 Start of command sequenceClear FIFOExecute CMD16 R

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1222 of 1658 REJ09B0261-0100 Start of command sequenceClear FIFOExecute CMD16 R

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1223 of 1658 REJ09B0261-0100 End of command sequenceYe sNoFFI interrupt detecte

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1224 of 1658 REJ09B0261-0100 Start of command sequenceClear FIFOExecute CMD16 R

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1225 of 1658 REJ09B0261-0100 End of command sequenceYe sNoFFI interrupt detecte

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1226 of 1658 REJ09B0261-0100 Start of command sequenceClear FIFORead response r

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1227 of 1658 REJ09B0261-0100 (6) Commands with Write Data Flash memory operati

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1228 of 1658 REJ09B0261-0100 • The end of the command sequence is detected by

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1229 of 1658 REJ09B0261-0100 MMCCLKMMCCMDMMCDATCMDSTRT(CMDSTART)(CMDI)CSTR(CWRE

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 96 of 1658 REJ09B0261-0100 5.4 Exception Types and Priorities Table 5.3 shows the types of exc

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1230 of 1658 REJ09B0261-0100 MMCCLKMMCCMDMMCDATCMDSTRT(CMDSTART)INTSTR0(CMDI)(C

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1231 of 1658 REJ09B0261-0100 MMCCLKMMCCMDMMCDATCMDSTRT(CMDSTART)INTSTR0(CMDI)(C

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1232 of 1658 REJ09B0261-0100 MMCCLKMMCCMDMMCDATCMDSTRT(CMDSTART)INTSTR0(CMDI)(C

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1233 of 1658 REJ09B0261-0100 Start of command sequenceClear FIFOExecute CMD16 R

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1234 of 1658 REJ09B0261-0100 Start of command sequenceClear FIFOExecute CMD16 R

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1235 of 1658 REJ09B0261-0100 NoEnd of command sequenceWrite data to FIFOSet DAT

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1236 of 1658 REJ09B0261-0100 Start of command sequenceClear FIFOExecute CMD16 S

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1237 of 1658 REJ09B0261-0100 NoEnd of command sequenceWrite data to FIFOSet DAT

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1238 of 1658 REJ09B0261-0100 Start of command sequenceClear FIFORead response r

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1239 of 1658 REJ09B0261-0100 24.5 MMCIF Interrupt Sources Table 24.7 lists the

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 97 of 1658 REJ09B0261-0100 Exception Transition Direction*3 Exception Category Execution Mode

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1240 of 1658 REJ09B0261-0100 24.6 Operations when Using DMA 24.6.1 Operation

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1241 of 1658 REJ09B0261-0100 • An error in a command sequence (during data rec

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1242 of 1658 REJ09B0261-0100 Start of command sequenceEnd of command sequenceCl

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1243 of 1658 REJ09B0261-0100 Start of command sequenceClear FIFOExecute CMD16Co

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1244 of 1658 REJ09B0261-0100 End of command sequenceSet DMACR to H'84Clear

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1245 of 1658 REJ09B0261-0100 Start of command sequenceClear FIFOExecute CMD16Co

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1246 of 1658 REJ09B0261-0100 End of command sequenceSet DMACR to H'84Clear

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1247 of 1658 REJ09B0261-0100 Start of command sequenceEnd of command sequenceCl

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1248 of 1658 REJ09B0261-0100 Start of command sequenceClear FIFOExecute CMD16Co

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1249 of 1658 REJ09B0261-0100 End of command sequenceSet DMACR to H'84Set C

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 98 of 1658 REJ09B0261-0100 5.5 Exception Flow 5.5.1 Exception Flow Figure 5.1 shows an outlin

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1250 of 1658 REJ09B0261-0100 24.6.2 Operation in Write Sequence To transfer da

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1251 of 1658 REJ09B0261-0100 • An error in a command sequence (during data tra

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1252 of 1658 REJ09B0261-0100 Start of command sequenceClear FIFOExecute CMD16Co

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1253 of 1658 REJ09B0261-0100 End of command sequenceSet CMDOFF to 1Set the DATA

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1254 of 1658 REJ09B0261-0100 Start of command sequenceClear FIFOExecute CMD16Co

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1255 of 1658 REJ09B0261-0100 End of command sequenceSet DATAEN to 1DRPI interru

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1256 of 1658 REJ09B0261-0100 Start of command sequenceClear FIFOExecute CMD16Co

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1257 of 1658 REJ09B0261-0100 End of command sequenceSet DATAEN to 1DRPI interru

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1258 of 1658 REJ09B0261-0100 Start of command sequenceClear FIFOConfigure the D

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1259 of 1658 REJ09B0261-0100 Start of command sequenceClear FIFOExecute CMD16Co

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 99 of 1658 REJ09B0261-0100 Execute next instructionIs highest- priority exceptionre-exceptionty

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1260 of 1658 REJ09B0261-0100 End of command sequenceBTI interrupt detected?NoYe

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1261 of 1658 REJ09B0261-0100 24.7 Register Accesses with Little Endian Specifi

24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1262 of 1658 REJ09B0261-0100

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1263 of 1658 REJ09B0261-0100 Section 25 Audio Codec Interface (HAC) The HAC, the au

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1264 of 1658 REJ09B0261-0100 Figure 25.1 shows a block diagram of the HAC. HAC receiv

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1265 of 1658 REJ09B0261-0100 25.2 Input/Output Pins Table 25.1 describes the HAC pin

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1266 of 1658 REJ09B0261-0100 25.3 Register Descriptions The following shows the HAC

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1267 of 1658 REJ09B0261-0100 Table 25.2 Register Configuration (2) Channel Register

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1268 of 1658 REJ09B0261-0100 Channel Register Name Abbrev. Power-on Reset by PRESET

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1269 of 1658 REJ09B0261-0100 25.3.1 Control and Status Register (HACCR) HACCR is a 3

Rev.1.00 Jan. 10, 2008 Page xiii of xxx REJ09B0261-0100 8.7 Store Queues...

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 100 of 1658 REJ09B0261-0100 5.5.2 Exception Source Acceptance A priority ranking is provided f

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1270 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 10 WMRT 0

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1271 of 1658 REJ09B0261-0100 25.3.2 Command/Status Address Register (HACCSAR) HACCSA

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1272 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 18 17 16 15

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1273 of 1658 REJ09B0261-0100 25.3.3 Command/Status Data Register (HACCSDR) HACCSDR i

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1274 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 20 ⎯

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1275 of 1658 REJ09B0261-0100 25.3.4 PCM Left Channel Register (HACPCML) HACPCML is a

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1276 of 1658 REJ09B0261-0100 In 16-bit packed DMA mode, HACPCML is defined as follows

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1277 of 1658 REJ09B0261-0100 25.3.5 PCM Right Channel Register (HACPCMR) HACPCMR is

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1278 of 1658 REJ09B0261-0100 25.3.6 TX Interrupt Enable Register (HACTIER) HACTIER i

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1279 of 1658 REJ09B0261-0100 25.3.7 TX Status Register (HACTSR) HACTSR is a 32-bit r

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 101 of 1658 REJ09B0261-0100 5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, ge

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1280 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W*2 Description 27 to 10 ⎯

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1281 of 1658 REJ09B0261-0100 25.3.8 RX Interrupt Enable Register (HACRIER) HACRIER i

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1282 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 12 PRRFOVIE

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1283 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W* Description 31 to 23 ⎯

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1284 of 1658 REJ09B0261-0100 25.3.10 HAC Control Register (HACACR) HACACR is a 32-bi

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1285 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 25 ⎯ 0 R Re

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1286 of 1658 REJ09B0261-0100 25.4 AC 97 Frame Slot Structure Figure 25.2 shows the A

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1287 of 1658 REJ09B0261-0100 Table 25.4 AC97 Receive Frame Structure Slot Name Desc

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1288 of 1658 REJ09B0261-0100 25.5 Operation 25.5.1 Receiver The HAC receiver receiv

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1289 of 1658 REJ09B0261-0100 25.5.3 DMA The HAC supports DMA transfer for slots 3 an

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 102 of 1658 REJ09B0261-0100 5.6 Description of Exceptions The various exception handling opera

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1290 of 1658 REJ09B0261-0100 25.5.5 Initialization Sequence Figure 25.3 shows an exa

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1291 of 1658 REJ09B0261-0100 NoNoYesYesYesWrite to codecReturn ErrorWrite 0 to TSR.CM

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1292 of 1658 REJ09B0261-0100 Read codecNoYesNoYesNoYesYesYesYesNoYesRegV = H'7C(

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1293 of 1658 REJ09B0261-0100 NoYesSend_read_requestWrite 0 to RSR.STARYWrite 0 to RSR

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1294 of 1658 REJ09B0261-0100 NoNoYesWaitLoop_CMDAMTNotes: E3, E4: Loop count req

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1295 of 1658 REJ09B0261-0100 25.5.6 Power-Down Mode It is possible to stop or resume

25. Audio Codec Interface (HAC) Rev.1.00 Jan. 10, 2008 Page 1296 of 1658 REJ09B0261-0100

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1297 of 1658 REJ09B0261-0100 Section 26 Serial Sound Interface (SSI) Module

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1298 of 1658 REJ09B0261-0100 Figure 26.1 is a block diagram of the SSI module

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1299 of 1658 REJ09B0261-0100 26.2 Input/Output Pins Table 26.1 lists the pin

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 103 of 1658 REJ09B0261-0100 (4) Instruction TLB Multiple Hit Exception • Source: Multiple ITL

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1300 of 1658 REJ09B0261-0100 26.3 Register Descriptions The SSI has the foll

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1301 of 1658 REJ09B0261-0100 26.3.1 Control Register (SSICR) SSICR is a 32-b

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1302 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 23 2

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1303 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 14

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1304 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 12

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1305 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 9 P

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1306 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 8 D

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1307 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 C

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1308 of 1658 REJ09B0261-0100 26.3.2 Status Register (SSISR) SSISR is configu

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1309 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 27 U

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 104 of 1658 REJ09B0261-0100 5.6.2 General Exceptions (1) Data TLB Miss Exception • Source: A

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1310 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 26 O

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1311 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 24

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1312 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 1 S

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1313 of 1658 REJ09B0261-0100 26.3.3 Transmit Data Register (SSITDR) SSITDR i

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1314 of 1658 REJ09B0261-0100 26.4 Operation 26.4.1 Bus Format The SSI modul

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1315 of 1658 REJ09B0261-0100 26.4.2 Non-Compressed Modes The non-compressed

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1316 of 1658 REJ09B0261-0100 1. Philips Format Figures 26.2 and 26.3 show the

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1317 of 1658 REJ09B0261-0100 2. Sony Format System word 1 System word 2Data w

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1318 of 1658 REJ09B0261-0100 Table 26.4 Number of Padding Bits for Each Vali

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1319 of 1658 REJ09B0261-0100 In the case of the SSI module configured as a tr

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 105 of 1658 REJ09B0261-0100 (2) Instruction TLB Miss Exception • Source: Address mismatch in

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1320 of 1658 REJ09B0261-0100 System word 2Dataword 1Dataword 2Dataword 3Dataw

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1321 of 1658 REJ09B0261-0100 (7) Configuration Fields—Signal Format Fields T

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1322 of 1658 REJ09B0261-0100 1. Inverted Clock System word 1 System word 2As

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1323 of 1658 REJ09B0261-0100 4. Padding Bits First, Followed by Serial Data,

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1324 of 1658 REJ09B0261-0100 7. Parallel Right Aligned with Delay As basic s

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1325 of 1658 REJ09B0261-0100 The word select pin in this mode does not act as

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1326 of 1658 REJ09B0261-0100 (1) Slave Receiver This mode allows the module

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1327 of 1658 REJ09B0261-0100 26.4.4 Operation Modes There are three modes of

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1328 of 1658 REJ09B0261-0100 26.4.5 Transmit Operation Transmission can be c

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1329 of 1658 REJ09B0261-0100 (1) Transmission Using DMA Controller NoYesYesS

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 106 of 1658 REJ09B0261-0100 (3) Initial Page Write Exception • Source: TLB is hit in a store

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1330 of 1658 REJ09B0261-0100 (2) Transmission using Interrupt Data Flow Cont

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1331 of 1658 REJ09B0261-0100 26.4.6 Receive Operation As with transmission t

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1332 of 1658 REJ09B0261-0100 (1) Reception Using DMA Controller StartEnd*Rel

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1333 of 1658 REJ09B0261-0100 (2) Reception Using Interrupt Data Flow Control

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1334 of 1658 REJ09B0261-0100 When an underflow or overflow error condition is

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1335 of 1658 REJ09B0261-0100 26.5 Usage Note 26.5.1 Restrictions when an Ov

26. Serial Sound Interface (SSI) Module Rev.1.00 Jan. 10, 2008 Page 1336 of 1658 REJ09B0261-0100 SCKSSI_WSSSI_SDATASSISR.IDSTSSICR.ENData transmi

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1337 of 1658 REJ09B0261-0100 Section 27 NAND Flash Memory Controller (FLCT

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1338 of 1658 REJ09B0261-0100 (5) Data Transfer FIFO • On-chip 224-byte FLD

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1339 of 1658 REJ09B0261-0100 Figure 27.1 shows a block diagram of the FLCTL.

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 107 of 1658 REJ09B0261-0100 (4) Data TLB Protection Violation Exception • Source: The access

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1340 of 1658 REJ09B0261-0100 27.2 Input/Output Pins Table 27.1 shows the pi

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1341 of 1658 REJ09B0261-0100 Corresponding Flash Memory Pin Pin Name Functi

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1342 of 1658 REJ09B0261-0100 27.3 Register Descriptions Table 27.2 shows th

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1343 of 1658 REJ09B0261-0100 Table 27.3 Register States in Each Processing

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1344 of 1658 REJ09B0261-0100 27.3.1 Common Control Register (FLCMNCR) FLCMN

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1345 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1346 of 1658 REJ09B0261-0100 27.3.2 Command Control Register (FLCMDCR) FLCM

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1347 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 25

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1348 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 16

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1349 of 1658 REJ09B0261-0100 27.3.4 Address Register (FLADR) FLADR is a 32-

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 108 of 1658 REJ09B0261-0100 The PC and SR contents for the instruction at which this exception

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1350 of 1658 REJ09B0261-0100 • Sector access mode 31 30 29 28 27 26 25 24 2

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1351 of 1658 REJ09B0261-0100 27.3.5 Address Register 2 (FLADR2) FLADR2 is a

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1352 of 1658 REJ09B0261-0100 27.3.6 Data Counter Register (FLDTCNTR) FLDTCN

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1353 of 1658 REJ09B0261-0100 27.3.7 Data Register (FLDATAR) FLDATAR is a 32

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1354 of 1658 REJ09B0261-0100 27.3.8 Interrupt DMA Control Register (FLINTDM

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1355 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 t

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1356 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 18 A

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1357 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7 BT

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1358 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 B

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1359 of 1658 REJ09B0261-0100 27.3.9 Ready Busy Timeout Setting Register (FL

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 109 of 1658 REJ09B0261-0100 (5) Instruction TLB Protection Violation Exception • Source: The

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1360 of 1658 REJ09B0261-0100 27.3.10 Ready Busy Timeout Counter (FLBSYCNT)

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1361 of 1658 REJ09B0261-0100 27.3.11 Data FIFO Register (FLDTFIFO) FLDTFIFO

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1362 of 1658 REJ09B0261-0100 27.3.12 Control Code FIFO Register (FLECFIFO)

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1363 of 1658 REJ09B0261-0100 27.3.13 Transfer Control Register (FLTRCR) Set

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1364 of 1658 REJ09B0261-0100 27.4 Operation 27.4.1 Operating Modes Two ope

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1365 of 1658 REJ09B0261-0100 Figures 27.3 and 27.4 show examples of writing

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1366 of 1658 REJ09B0261-0100 (2) NAND-Type Flash Memory Access (2048 + 64 B

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1367 of 1658 REJ09B0261-0100 Figures 27.6 and 27.7 show examples of writing

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1368 of 1658 REJ09B0261-0100 27.4.3 Sector Access Mode In sector access mod

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1369 of 1658 REJ09B0261-0100 (1) Physical Sector Figure 27.9 shows the rela

Rev.1.00 Jan. 10, 2008 Page xiv of xxx REJ09B0261-0100 10.4 Interrupt Sources...

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 110 of 1658 REJ09B0261-0100 ITLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS;

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1370 of 1658 REJ09B0261-0100 (2) Continuous Sector Access Continuous physic

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1371 of 1658 REJ09B0261-0100 27.4.4 Status Read The FLCTL can read the stat

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1372 of 1658 REJ09B0261-0100 (2) Status Read of NAND-Type Flash Memory (204

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1373 of 1658 REJ09B0261-0100 27.5 Example of Register Setting The examples

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1374 of 1658 REJ09B0261-0100 Start of sector access (flash write)FLTRCR.TREN

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1375 of 1658 REJ09B0261-0100 Start of command access (flash read)FLTRCR.TREN

27. NAND Flash Memory Controller (FLCTL) Rev.1.00 Jan. 10, 2008 Page 1376 of 1658 REJ09B0261-0100 27.6 Interrupt Processing The FLCTL has four i

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1377 of 1658 REJ09B0261-0100 Section 28 General Purpose I/O Ports (GPIO) 28.1

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1378 of 1658 REJ09B0261-0100 Table 28.1 Multiplexed Pins Controlled by Port Con

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1379 of 1658 REJ09B0261-0100 Pin Name Port GPIO Selectable Module GPIO Inter

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 111 of 1658 REJ09B0261-0100 • Transition operations: The virtual address (32 bits) at which th

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1380 of 1658 REJ09B0261-0100 Pin Name Port GPIO Selectable Module GPIO Inter

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1381 of 1658 REJ09B0261-0100 Pin Name Port GPIO Selectable Module GPIO Inter

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1382 of 1658 REJ09B0261-0100 28.2 Register Descriptions The following registers

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1383 of 1658 REJ09B0261-0100 Register Name Abbrev. R/W P4 Address*1Area 7 Add

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1384 of 1658 REJ09B0261-0100 Table 28.2 Register Configuration (2) Register Na

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1385 of 1658 REJ09B0261-0100 Register Name Abbrev. Power-on Reset by RESET Pin/

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1386 of 1658 REJ09B0261-0100 28.2.1 Port A Control Register (PACR) PACR is a 16

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1387 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 9 8 PA4M

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1388 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 1 0 PA0M

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1389 of 1658 REJ09B0261-0100 28.2.2 Port B Control Register (PBCR) PBCR is a 16

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 112 of 1658 REJ09B0261-0100 (7) Instruction Address Error • Sources: ⎯ Instruction fetch fro

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1390 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 9 8 PB4M

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1391 of 1658 REJ09B0261-0100 28.2.3 Port C Control Register (PCCR) PCCR is a 16

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1392 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PC3M

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1393 of 1658 REJ09B0261-0100 28.2.4 Port D Control Register (PDCR) PDCR is a 16

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1394 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PD3M

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1395 of 1658 REJ09B0261-0100 28.2.5 Port E Control Register (PECR) PECR is a 16

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1396 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 5 4 PE2M

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1397 of 1658 REJ09B0261-0100 28.2.6 Port F Control Register (PFCR) PFCR is a 16

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1398 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PF3M

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1399 of 1658 REJ09B0261-0100 28.2.7 Port G Control Register (PGCR) PGCR is a 16

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 113 of 1658 REJ09B0261-0100 (8) Unconditional Trap • Source: Execution of TRAPA instruction •

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1400 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PG3M

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1401 of 1658 REJ09B0261-0100 28.2.8 Port H Control Register (PHCR) PHCR is a 16

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1402 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PH3M

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1403 of 1658 REJ09B0261-0100 28.2.9 Port J Control Register (PJCR) PJCR is a 16

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1404 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PJ3M

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1405 of 1658 REJ09B0261-0100 28.2.10 Port K Control Register (PKCR) PKCR is a 1

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1406 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PK3M

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1407 of 1658 REJ09B0261-0100 28.2.11 Port L Control Register (PLCR) PLCR is a 1

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1408 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PL3M

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1409 of 1658 REJ09B0261-0100 28.2.12 Port M Control Register (PMCR) PMCR is a 1

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 114 of 1658 REJ09B0261-0100 (9) General Illegal Instruction Exception • Sources: ⎯ Decoding

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1410 of 1658 REJ09B0261-0100 28.2.13 Port N Control Register (PNCR) PNCR is a 1

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1411 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PL3M

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1412 of 1658 REJ09B0261-0100 28.2.14 Port P Control Register (PPCR) PPCR is a 1

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1413 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 7 6 PP3M

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1414 of 1658 REJ09B0261-0100 28.2.15 Port Q Control Register (PQCR) PQCR is a 1

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1415 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 5 4 PQ2M

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1416 of 1658 REJ09B0261-0100 28.2.16 Port R Control Register (PRCR) PRCR is a 1

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1417 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 3 2 PR1M

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1418 of 1658 REJ09B0261-0100 28.2.17 Port A Data Register (PADR) PADR is an 8-b

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1419 of 1658 REJ09B0261-0100 28.2.18 Port B Data Register (PBDR) PBDR is an 8-b

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 115 of 1658 REJ09B0261-0100 (10) Slot Illegal Instruction Exception • Sources: ⎯ Decoding of

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1420 of 1658 REJ09B0261-0100 28.2.19 Port C Data Register (PCDR) PCDR is an 8-b

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1421 of 1658 REJ09B0261-0100 28.2.20 Port D Data Register (PDDR) PDDR is an 8-b

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1422 of 1658 REJ09B0261-0100 28.2.21 Port E Data Register (PEDR) PEDR is an 8-b

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1423 of 1658 REJ09B0261-0100 28.2.22 Port F Data Register (PFDR) PFDR is an 8-b

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1424 of 1658 REJ09B0261-0100 28.2.23 Port G Data Register (PGDR) PGDR is an 8-b

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1425 of 1658 REJ09B0261-0100 28.2.24 Port H Data Register (PHDR) PHDR is an 8-b

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1426 of 1658 REJ09B0261-0100 28.2.25 Port J Data Register (PJDR) PJDR is an 8-b

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1427 of 1658 REJ09B0261-0100 28.2.26 Port K Data Register (PKDR) PKDR is an 8-b

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1428 of 1658 REJ09B0261-0100 28.2.27 Port L Data Register (PLDR) PLDR is an 8-b

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1429 of 1658 REJ09B0261-0100 28.2.28 Port M Data Register (PMDR) PMDR is an 8-b

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 116 of 1658 REJ09B0261-0100 (11) General FPU Disable Exception • Source: Decoding of an FPU i

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1430 of 1658 REJ09B0261-0100 28.2.29 Port N Data Register (PNDR) PNDR is an 8-b

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1431 of 1658 REJ09B0261-0100 28.2.30 Port P Data Register (PPDR) PPDR is an 8-b

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1432 of 1658 REJ09B0261-0100 28.2.31 Port Q Data Register (PQDR) PQDR is an 8-b

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1433 of 1658 REJ09B0261-0100 28.2.32 Port R Data Register (PRDR) PRDR is an 8-b

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1434 of 1658 REJ09B0261-0100 28.2.33 Port E Pull-Up Control Register (PEPUPR) P

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1435 of 1658 REJ09B0261-0100 28.2.34 Port H Pull-Up Control Register (PHPUPR) P

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1436 of 1658 REJ09B0261-0100 28.2.35 Port J Pull-Up Control Register (PJPUPR) P

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1437 of 1658 REJ09B0261-0100 28.2.36 Port K Pull-Up Control Register (PKPUPR) P

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1438 of 1658 REJ09B0261-0100 28.2.37 Port L Pull-Up Control Register (PLPUPR) P

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1439 of 1658 REJ09B0261-0100 28.2.38 Port M Pull-Up Control Register (PMPUPR) P

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 117 of 1658 REJ09B0261-0100 (12) Slot FPU Disable Exception • Source: Decoding of an FPU inst

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1440 of 1658 REJ09B0261-0100 28.2.39 Port N Pull-Up Control Register (PNPUPR) P

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1441 of 1658 REJ09B0261-0100 28.2.40 Input-Pin Pull-Up Control Register 1 (PPUP

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1442 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 15 to 8

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1443 of 1658 REJ09B0261-0100 28.2.42 Peripheral Module Select Register 1 (P1MSE

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1444 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 12 11 PM

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1445 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 6 5 P1MS

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1446 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 0 P1MSE

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1447 of 1658 REJ09B0261-0100 28.2.43 Peripheral Module Select Register 2 (P2MSE

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1448 of 1658 REJ09B0261-0100 Bit Bit Name Initial value R/W Description 15 to 3

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1449 of 1658 REJ09B0261-0100 28.3 Usage Example Setting procedure examples are

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 118 of 1658 REJ09B0261-0100 (13) Pre-Execution User Break/Post-Execution User Break • Source:

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1450 of 1658 REJ09B0261-0100 28.3.2 Port Input function To input the data via t

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1451 of 1658 REJ09B0261-0100 28.3.3 Peripheral Module Function The procedures f

28. General Purpose I/O Ports (GPIO) Rev.1.00 Jan. 10, 2008 Page 1452 of 1658 REJ09B0261-0100

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1453 of 1658 REJ09B0261-0100 Section 29 User Break Controller (UBC) The user break

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1454 of 1658 REJ09B0261-0100 Figure 29.1 shows the UBC block diagram. SABInternal bus

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1455 of 1658 REJ09B0261-0100 29.2 Register Descriptions The UBC has the following re

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1456 of 1658 REJ09B0261-0100 Table 29.2 Register Status in Each Processing State Reg

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1457 of 1658 REJ09B0261-0100 29.2.1 Match Condition Setting Registers 0 and 1 (CBR0

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1458 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 29 to 24 MFI

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1459 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7, 6 CD All

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 119 of 1658 REJ09B0261-0100 (14) FPU Exception • Source: Exception due to execution of a floa

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1460 of 1658 REJ09B0261-0100 • CBR1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 160

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1461 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 23 to 16 AIV

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1462 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7, 6 CD All

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1463 of 1658 REJ09B0261-0100 29.2.2 Match Operation Setting Registers 0 and 1 (CRR0

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1464 of 1658 REJ09B0261-0100 • CRR1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 160

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1465 of 1658 REJ09B0261-0100 29.2.3 Match Address Setting Registers 0 and 1 (CAR0 an

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1466 of 1658 REJ09B0261-0100 29.2.4 Match Address Mask Setting Registers 0 and 1 (CA

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1467 of 1658 REJ09B0261-0100 • CAMR1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1468 of 1658 REJ09B0261-0100 29.2.5 Match Data Setting Register 1 (CDR1) CDR1 is a r

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1469 of 1658 REJ09B0261-0100 29.2.6 Match Data Mask Setting Register 1 (CDMR1) CDMR1

Rev.1.00 Jan. 10, 2008 Page xv of xxx REJ09B0261-0100 11.5.9 Bus Arbitration ...

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 120 of 1658 REJ09B0261-0100 5.6.3 Interrupts (1) NMI (Nonmaskable Interrupt) • Source: NMI p

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1470 of 1658 REJ09B0261-0100 29.2.7 Execution Count Break Register 1 (CETR1) CETR1 i

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1471 of 1658 REJ09B0261-0100 29.2.8 Channel Match Flag Register (CCMFR) CCMFR is a r

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1472 of 1658 REJ09B0261-0100 29.2.9 Break Control Register (CBCR) CBCR is a readable

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1473 of 1658 REJ09B0261-0100 29.3 Operation Description 29.3.1 Definition of Words

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1474 of 1658 REJ09B0261-0100 29.3.2 User Break Operation Sequence The following desc

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1475 of 1658 REJ09B0261-0100 6. While the BL bit in the SR register is 1, no break r

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1476 of 1658 REJ09B0261-0100 29.3.4 Operand Access Cycle Break 1. Table 29.4 shows

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1477 of 1658 REJ09B0261-0100 4. If the operand bus is selected, a break occurs after

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1478 of 1658 REJ09B0261-0100 • When the match condition is satisfied at the instruct

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1479 of 1658 REJ09B0261-0100 29.3.6 Program Counter Value to be Saved When a break h

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 121 of 1658 REJ09B0261-0100 The code corresponding to the each interrupt source is set in INTEV

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1480 of 1658 REJ09B0261-0100 29.4 User Break Debugging Support Function By using the

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1481 of 1658 REJ09B0261-0100 29.5 User Break Examples (1) Match Conditions Are Spec

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1482 of 1658 REJ09B0261-0100 With the above settings, the user break occurs after exe

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1483 of 1658 REJ09B0261-0100 With the above settings, the user break occurs after exe

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1484 of 1658 REJ09B0261-0100 ⎯ Channel 1 Address: H'00008010 / Address mask: H&

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1485 of 1658 REJ09B0261-0100 29.6 Usage Notes 1. A desired break may not occur betw

29. User Break Controller (UBC) Rev.1.00 Jan. 10, 2008 Page 1486 of 1658 REJ09B0261-0100 ⎯ If the post-instruction-execution break and data acce

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1487 of 1658 REJ09B0261-0100 Section 30 User Debugging Interface (H-UDI) The H

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1488 of 1658 REJ09B0261-0100 TDOTDITRSTTMSTCKSDIR ASEBRK/BRKACKBoundary-scanTAPc

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1489 of 1658 REJ09B0261-0100 30.2 Input/Output Pins Table 30.1 shows the pin co

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 122 of 1658 REJ09B0261-0100 8. Initial page write exception in second data transfer (2) Indi

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1490 of 1658 REJ09B0261-0100 Notes: 1. This pin is pulled up in the chip. In d

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1491 of 1658 REJ09B0261-0100 30.3 Register Description The H-UDI has the follow

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1492 of 1658 REJ09B0261-0100 30.3.1 Instruction Register (SDIR) SDIR is a 16-bi

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1493 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 to 1

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1494 of 1658 REJ09B0261-0100 Table 30.5 Boundary Scan Register Configuration Nu

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1495 of 1658 REJ09B0261-0100 Number Pin Name Type Number Pin Name Type 49

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1496 of 1658 REJ09B0261-0100 Number Pin Name Type Number Pin Name Type 43

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1497 of 1658 REJ09B0261-0100 Number Pin Name Type Number Pin Name Type 37

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1498 of 1658 REJ09B0261-0100 Number Pin Name Type Number Pin Name Type 30

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1499 of 1658 REJ09B0261-0100 Number Pin Name Type Number Pin Name Type 24

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 123 of 1658 REJ09B0261-0100 5.7 Usage Notes (1) Return from Exception Handling A. Check the

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1500 of 1658 REJ09B0261-0100 Number Pin Name Type Number Pin Name Type 18

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1501 of 1658 REJ09B0261-0100 Number Pin Name Type Number Pin Name Type 11

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1502 of 1658 REJ09B0261-0100 Number Pin Name Type Number Pin Name Type 55 SC

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1503 of 1658 REJ09B0261-0100 30.4 Operation 30.4.1 Boundary-Scan TAP Controlle

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1504 of 1658 REJ09B0261-0100 00010000Test-Logic-ResetRun-Test-IdleRun-Test-IdleT

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1505 of 1658 REJ09B0261-0100 30.4.2 TAP Control Figure 30.3 shows the internal

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1506 of 1658 REJ09B0261-0100 30.4.3 H-UDI Reset The H-UDI is reset by a power-o

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1507 of 1658 REJ09B0261-0100 30.4.4 H-UDI Interrupt The H-UDI interrupt functio

30. User Debugging Interface (H-UDI) Rev.1.00 Jan. 10, 2008 Page 1508 of 1658 REJ09B0261-0100

31. Register List Rev.1.00 Jan. 10, 2008 Page 1509 of 1658 REJ09B0261-0100 Section 31 Register List This section is a summary of the contents o

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 124 of 1658 REJ09B0261-0100 other exceptions is determined depending on the processing mode by

31. Register List Rev.1.00 Jan. 10, 2008 Page 1510 of 1658 REJ09B0261-0100 Table 31.1 Register Address List Module Name Name Abbreviation R/W P

31. Register List Rev.1.00 Jan. 10, 2008 Page 1511 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1512 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1513 of 1658 REJ09B0261-0100 Modul e Name Name Abbreviation R/W P4 Area Address Area 7 Address Acc

31. Register List Rev.1.00 Jan. 10, 2008 Page 1514 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1515 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1516 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1517 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1518 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1519 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 125 of 1658 REJ09B0261-0100 Section 6 Floating-Point Unit (FPU) 6.1 Features The FPU

31. Register List Rev.1.00 Jan. 10, 2008 Page 1520 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1521 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1522 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1523 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1524 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1525 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1526 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1527 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1528 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1529 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 126 of 1658 REJ09B0261-0100 6.2 Data Formats 6.2.1 Floating-Point Format A floating-po

31. Register List Rev.1.00 Jan. 10, 2008 Page 1530 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1531 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1532 of 1658 REJ09B0261-0100 Module Name Name Abbreviation R/W P4 Area Address Area 7 Address Acce

31. Register List Rev.1.00 Jan. 10, 2008 Page 1533 of 1658 REJ09B0261-0100 31.2 States of the Registers in the Individual Operating Modes The s

31. Register List Rev.1.00 Jan. 10, 2008 Page 1534 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1535 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1536 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1537 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1538 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1539 of 1658 REJ09B0261-0100 Table 31.3 States of the Registers in the Individual Operating Modes

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 127 of 1658 REJ09B0261-0100 Table 6.1 Floating-Point Number Formats and Parameters Para

31. Register List Rev.1.00 Jan. 10, 2008 Page 1540 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1541 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1542 of 1658 REJ09B0261-0100 Table 31.4 States of the Registers in the Individual Operating Modes

31. Register List Rev.1.00 Jan. 10, 2008 Page 1543 of 1658 REJ09B0261-0100 Table 31.5 States of the Registers in the Individual Operating Modes

31. Register List Rev.1.00 Jan. 10, 2008 Page 1544 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1545 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1546 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1547 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1548 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1549 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 128 of 1658 REJ09B0261-0100 Table 6.2 Floating-Point Ranges Type Single-Precision Doubl

31. Register List Rev.1.00 Jan. 10, 2008 Page 1550 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1551 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1552 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1553 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1554 of 1658 REJ09B0261-0100 Table 31.6 States of the Registers in the Individual Operating Modes

31. Register List Rev.1.00 Jan. 10, 2008 Page 1555 of 1658 REJ09B0261-0100 Table 31.7 States of the Registers in the Individual Operating Modes

31. Register List Rev.1.00 Jan. 10, 2008 Page 1556 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1557 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1558 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

31. Register List Rev.1.00 Jan. 10, 2008 Page 1559 of 1658 REJ09B0261-0100 Module Name Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manu

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 129 of 1658 REJ09B0261-0100 6.2.2 Non-Numbers (NaN) Figure 6.3 shows the bit pattern of

31. Register List Rev.1.00 Jan. 10, 2008 Page 1560 of 1658 REJ09B0261-0100 Table 31.8 States of the Registers in the Individual Operating Modes

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1561 of 1658 REJ09B0261-0100 Section 32 Electrical Characteristics 32.1 Absolute Ma

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1562 of 1658 REJ09B0261-0100 32.2 DC Characteristics Table 32.2 DC Characteristics (

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1563 of 1658 REJ09B0261-0100 Item Symbol Min. Typ. Max. Unit Test Conditions PRESET, N

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1564 of 1658 REJ09B0261-0100 Item Symbol Min. Typ. Max. Unit Item AC differential

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1565 of 1658 REJ09B0261-0100 Item Symbol Min. Typ. Max. Unit Test Conditions PCI p

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1566 of 1658 REJ09B0261-0100 Table 32.3 Permissible Output Currents Item Symbol Min.

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1567 of 1658 REJ09B0261-0100 32.3 AC Characteristics In principle, this LSI's in

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1568 of 1658 REJ09B0261-0100 32.3.1 Clock and Control Signal Timing Table 32.6 Clock

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1569 of 1658 REJ09B0261-0100 Item Symbol Min. Max. Unit Figure MODE13 to MODE11, MODE8

Rev.1.00 Jan. 10, 2008 Page xvi of xxx REJ09B0261-0100 12.5.11 Method for Securing Time Required for Initialization, Self-Refresh Cancellation, e

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 130 of 1658 REJ09B0261-0100 See section 10, Instruction Descriptions of the SH-4A Extend

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1570 of 1658 REJ09B0261-0100 tCKOcyctCKOH1tCKOL1tCKOrtCKOf1/2VDDQVOHVOHVOLVOLVOH1/2VDD

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1571 of 1658 REJ09B0261-0100 VDDtOSC1VDDmintMDRHtOSCMDtTRSTRHtRESWCLKOUTNotes: 1. Os

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1572 of 1658 REJ09B0261-0100 tMDRHPRESETMODE13 to MODE11MODE8 to MODE5tMDRStPRrtPRf Fi

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1573 of 1658 REJ09B0261-0100 tBREQHtBREQStBREQHtBREQStBACKDtBACKDtBOFF1tBON1CKIOBREQBA

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1574 of 1658 REJ09B0261-0100 32.3.3 Bus Timing Table 32.8 Bus Timing Conditions: VDD

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1575 of 1658 REJ09B0261-0100 CLKOUTA25 to A0CSnRDRD/WRD31 to D0D31 to D0(Write)(Read)D

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1576 of 1658 REJ09B0261-0100 A25 to A0D31 to D0D31 to D0(Write)(Read)(SA: IO ← memory)

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1577 of 1658 REJ09B0261-0100 A25 to A0D31 to D0D31 to D0(Write)(Read)(SA: IO ← memory)

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1578 of 1658 REJ09B0261-0100 A25 to A0D31 to D0D31 to D0(Write)(Read)(SA: IO ← memory)

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1579 of 1658 REJ09B0261-0100 D31 to D0(Read)(SA: IO ← memory) Legend:IO: DACK deviceSA

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 131 of 1658 REJ09B0261-0100 6.3 Register Descriptions 6.3.1 Floating-Point Registers F

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1580 of 1658 REJ09B0261-0100 D31 to D0(Read)(SA: IO ← memory) Legend:IO: DACK deviceSA

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1581 of 1658 REJ09B0261-0100 D31 to D0(Read)(SA: IO ← memory) Legend:IO: DACK deviceSA

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1582 of 1658 REJ09B0261-0100 D31 to D0(Read)(SA: IO ← memory) Legend:IO: DACK deviceSA

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1583 of 1658 REJ09B0261-0100 D15 to D0D15 to D0(Write)(Read)Legend:IO: DACK deviceSA:

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1584 of 1658 REJ09B0261-0100 D15 to D0D15 to D0(Write)(Read)Legend:IO: DACK deviceSA:

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1585 of 1658 REJ09B0261-0100 Tpci0 Tpci1Tpci2wTpci2Tpci1w Tpci0 Tpci1Tpci2wTpci2Tpci1w

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1586 of 1658 REJ09B0261-0100 Tm1 Tmd1w Tmd1 Tm0 Tmd1w Tmd1Tmd1wCLKOUTRD/FRAMERD/WRWEnR

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1587 of 1658 REJ09B0261-0100 Tm1 Tmd1w Tmd1tFMDtFMDtBSDtBSDtCSDtCSDtDACDtRDYHtRDYStDAC

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1588 of 1658 REJ09B0261-0100 D31 to D0(2) 1st data: No internal wait, 2nd to 8th data:

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1589 of 1658 REJ09B0261-0100 D31 to D0(2) 1st data: One internal wait cycle, 2nd to 8t

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 132 of 1658 REJ09B0261-0100 7. Single-precision floating-point extended register matrix

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1590 of 1658 REJ09B0261-0100 A25 to A0D31 to D0(Read)(SA: IO ← memory) Legend:IO: DACK

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1591 of 1658 REJ09B0261-0100 A25 to A0D31 to D0(Read)(SA: IO ← memory) Legend:IO: DACK

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1592 of 1658 REJ09B0261-0100 32.3.4 DBSC2 Signal Timing Table 32.9 DBSC2 Signal Timi

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1593 of 1658 REJ09B0261-0100 Item Symbol Min. Max. Unit Figure Notes Write command to

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1594 of 1658 REJ09B0261-0100 MCK0, MCK1 (solid line)MCK0, MCK1 (dotted line)tIHMCKE, M

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1595 of 1658 REJ09B0261-0100 MDQS[3:0] (solid line)MDQS[3:0] (dotted line)tRDQSHtRPREt

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1596 of 1658 REJ09B0261-0100 MDQS[3:0] (solid line)MDQS[3:0] (dotted line)MDQ[31:0]MDM

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1597 of 1658 REJ09B0261-0100 32.3.5 INTC Module Signal Timing Table 32.10 INTC Modul

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1598 of 1658 REJ09B0261-0100 NMIIRQtNMIIHtNMIILtIRQIHtIRQIL Figure 32.35 Interrupt S

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1599 of 1658 REJ09B0261-0100 32.3.6 PCIC Module Signal Timing Table 32.11 PCIC Signa

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 133 of 1658 REJ09B0261-0100 6.3.2 Floating-Point Status/Control Register (FPSCR) 31 30

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1600 of 1658 REJ09B0261-0100 0.5VDDQ0.5VDDQtPCICYCtPCIHIGHtPCILOWtPCIftPCIrVLVLVHVHVH

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1601 of 1658 REJ09B0261-0100 tPCISU0.4VDDQPCICLKInput0.4VDDQtPCIH Figure 32.39 PCI I

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1602 of 1658 REJ09B0261-0100 32.3.8 TMU Module Signal Timing Table 32.13 TMU Module

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1603 of 1658 REJ09B0261-0100 32.3.9 SCIF Module Signal Timing Table 32.14 SCIF Modul

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1604 of 1658 REJ09B0261-0100 tScyctTXDtRXStRXHSCIFn_CLKSCIFn_TXDSCIFn_RXDtTXD Figure 3

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1605 of 1658 REJ09B0261-0100 32.3.10 H-UDI Module Signal Timing Table 32.15 H-UDI Mo

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1606 of 1658 REJ09B0261-0100 ASEBRKBRKACKRESETtASEBRKHtASEBRKS Figure 32.45 RESET Ho

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1607 of 1658 REJ09B0261-0100 32.3.11 GPIO Signal Timing Table 32.16 GPIO Signal Timi

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1608 of 1658 REJ09B0261-0100 32.3.12 HSPI Module Signal Timing Table 32.17 HSPI Modu

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1609 of 1658 REJ09B0261-0100 32.3.13 SIOF Module Signal Timing Table 32.18 SIOF Modu

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 134 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 17 to 12 Cause

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1610 of 1658 REJ09B0261-0100 SIOF_SCK (Output)SIOF_SYNC (Output)SIOF_TXDSIOF_RXDtFSDtF

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1611 of 1658 REJ09B0261-0100 SIOF_SCK (Output)SIOF_SYNC (Output)SIOF_TXDSIOF_RXDtFSDtF

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1612 of 1658 REJ09B0261-0100 SIOF_SCK (Output)SIOF_SYNC (Output)SIOF_TXDSIOF_RXDtSICYC

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1613 of 1658 REJ09B0261-0100 32.3.14 MMCIF Module Signal Timing Table 32.19 MMCIF Mo

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1614 of 1658 REJ09B0261-0100 tMMRCStMMRCHMMCCLKMMCCMD (Input)MMCDAT (Input)tMMRDStMMRD

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1615 of 1658 REJ09B0261-0100 HACn_SYNCHACn_BITCLKtSYN_HIGH Figure 32.59 HAC Warm Res

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1616 of 1658 REJ09B0261-0100 32.3.16 SSI Interface Module Signal Timing Table 32.21

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1617 of 1658 REJ09B0261-0100 tDTRtHTRSSIn_SCKSSIn_WSSSIn_SDATA Figure 32.64 SSI Tran

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1618 of 1658 REJ09B0261-0100 32.3.17 FLCTL Module Signal Timing Table 32.22 NAND-Typ

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1619 of 1658 REJ09B0261-0100 FCE(Low)(High)(High)FCLEFR/BFD7 to FD0FREFWEFALECommandtN

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 135 of 1658 REJ09B0261-0100 <Big endian>DR (2i)FR (2i) FR (2i+1)8n+4 8n+78n 8n+363

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1620 of 1658 REJ09B0261-0100 FD7 to FD0(Low)(Low)(High)FCEFCLEFALEFWEFREFR/BtNRBDR2tNA

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1621 of 1658 REJ09B0261-0100 FCEFCLEFALEFREFR/BFD7 to FD0FWE(Low)(Low)(High)tNCDStNDOS

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1622 of 1658 REJ09B0261-0100 32.3.18 Display Unit Signal Timing Table 32.23 PCICLK/D

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1623 of 1658 REJ09B0261-0100 Table 32.25 Classification of Pins Pin Classification Di

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1624 of 1658 REJ09B0261-0100 tDStDHPCICLK/DCLKIN (Input)Display input control signal*1

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1625 of 1658 REJ09B0261-0100 tEXHLWtEXHHWtEXVHWtOD1tOD2IRDY/HSYNC(Input)IRDY/HSYNC(Inp

32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1626 of 1658 REJ09B0261-0100 The following figure shows the output load circuit. IOLIO

Appendix Rev.1.00 Jan. 10, 2008 Page 1627 of 1658 REJ09B0261-0100 Appendix A. Package Dimensions Figure A.1 Package Dimensions (436-Pin BGA) Note

Appendix Rev.1.00 Jan. 10, 2008 Page 1628 of 1658 REJ09B0261-0100 B. Mode Pin Settings The MODE14–MODE0 pin values are input in the event of a pow

Appendix Rev.1.00 Jan. 10, 2008 Page 1629 of 1658 REJ09B0261-0100 Table B.2 Area 0 Memory Type and Bus Width Pin Value MODE7 MODE6* MODE5 Mem

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 136 of 1658 REJ09B0261-0100 Table 6.3 Bit Allocation for FPU Exception Handling Field

Appendix Rev.1.00 Jan. 10, 2008 Page 1630 of 1658 REJ09B0261-0100 Table B.6 Bus Mode Pin Value MODE12 MODE11 Bus Mode L L PCI host bus bridge

Appendix Rev.1.00 Jan. 10, 2008 Page 1631 of 1658 REJ09B0261-0100 C. Pin Functions C.1 Pin States Table C.1 Pin States in Reset, Power-Down State,

Appendix Rev.1.00 Jan. 10, 2008 Page 1632 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O

Appendix Rev.1.00 Jan. 10, 2008 Page 1633 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O

Appendix Rev.1.00 Jan. 10, 2008 Page 1634 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O Po

Appendix Rev.1.00 Jan. 10, 2008 Page 1635 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O Po

Appendix Rev.1.00 Jan. 10, 2008 Page 1636 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O

Appendix Rev.1.00 Jan. 10, 2008 Page 1637 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O P

Appendix Rev.1.00 Jan. 10, 2008 Page 1638 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O

Appendix Rev.1.00 Jan. 10, 2008 Page 1639 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 137 of 1658 REJ09B0261-0100 6.4 Rounding In a floating-point instruction, rounding is p

Appendix Rev.1.00 Jan. 10, 2008 Page 1640 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O

Appendix Rev.1.00 Jan. 10, 2008 Page 1641 of 1658 REJ09B0261-0100 Reset Pin Name (LSI level) Pin Name (Module level) Related Module I/O

Appendix Rev.1.00 Jan. 10, 2008 Page 1642 of 1658 REJ09B0261-0100 C.2 Handling of Unused Pins Table C.2 Treatment of Unused Pins Pin Name (LSI le

Appendix Rev.1.00 Jan. 10, 2008 Page 1643 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use Port

Appendix Rev.1.00 Jan. 10, 2008 Page 1644 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use MCL

Appendix Rev.1.00 Jan. 10, 2008 Page 1645 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use AD[1

Appendix Rev.1.00 Jan. 10, 2008 Page 1646 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use PCIF

Appendix Rev.1.00 Jan. 10, 2008 Page 1647 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use TRDY

Appendix Rev.1.00 Jan. 10, 2008 Page 1648 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use MODE

Appendix Rev.1.00 Jan. 10, 2008 Page 1649 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use MODE

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 138 of 1658 REJ09B0261-0100 6.5 Floating-Point Exceptions 6.5.1 General FPU Disable Ex

Appendix Rev.1.00 Jan. 10, 2008 Page 1650 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use Port

Appendix Rev.1.00 Jan. 10, 2008 Page 1651 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use Port

Appendix Rev.1.00 Jan. 10, 2008 Page 1652 of 1658 REJ09B0261-0100 Pin Name (LSI level) Pin Name (Module level) Module I/O When Not in Use AUDC

Appendix Rev.1.00 Jan. 10, 2008 Page 1653 of 1658 REJ09B0261-0100 D. Turning On and Off Power Supply D.1 Turning On and Off Between Each Power Su

Appendix Rev.1.00 Jan. 10, 2008 Page 1654 of 1658 REJ09B0261-0100 D.2 Power-On and Power-Off Sequences for Power Supplies with Different Potential

Appendix Rev.1.00 Jan. 10, 2008 Page 1655 of 1658 REJ09B0261-0100 D.3 Turning On and Off Between the Same Power Supply Series The order of the pow

Appendix Rev.1.00 Jan. 10, 2008 Page 1656 of 1658 REJ09B0261-0100 E. Version Registers (PVR, PRR) The SH7785 has the read-only registers which sho

Appendix Rev.1.00 Jan. 10, 2008 Page 1657 of 1658 REJ09B0261-0100 F. Product Lineup Table F.1 SH7785 Product Lineup Product Type Voltage Operating

Appendix Rev.1.00 Jan. 10, 2008 Page 1658 of 1658 REJ09B0261-0100

Renesas 32-Bit RISC MicrocomputerHardware ManualSH7785Publication Date: Rev.1.00, January 10, 2008Published by: Sales Strategic Pla

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 139 of 1658 REJ09B0261-0100 6.5.3 FPU Exception Handling FPU exception handling is init

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japanhttp://www.renesas.comRefer to

SH7785 Hardware Manual

Rev.1.00 Jan. 10, 2008 Page xvii of xxx REJ09B0261-0100 14.4.2 Channel Priority...

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 140 of 1658 REJ09B0261-0100 6.6 Graphics Support Functions This LSI supports two kinds

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 141 of 1658 REJ09B0261-0100 (2) FTRV XMTRX, FVn (n: 0, 4, 8, 12) This instruction is ba

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 142 of 1658 REJ09B0261-0100 This instruction changes the value of the SZ bit in FPSCR,

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 143 of 1658 REJ09B0261-0100 Section 7 Memory Management Unit (MMU) This LSI support

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 144 of 1658 REJ09B0261-0100 7.1 Overview of MMU The MMU was conceived as a means of

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 145 of 1658 REJ09B0261-0100 There are two methods by which the MMU can perform mappin

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 146 of 1658 REJ09B0261-0100 7.1.1 Address Spaces (1) Virtual Address Space This LSI

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 147 of 1658 REJ09B0261-0100 Area 0Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7Phy

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 148 of 1658 REJ09B0261-0100 (b) P1 Area The P1 area does not allow address translati

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 149 of 1658 REJ09B0261-0100 The area from H'E000 0000 to H'E3FF FFFF compri

Rev.1.00 Jan. 10, 2008 Page xviii of xxx REJ09B0261-0100 16.4.1 Reset Request ...

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 150 of 1658 REJ09B0261-0100 (2) Physical Address Space This LSI supports a 29-bit ph

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 151 of 1658 REJ09B0261-0100 the return from the exception handling routine, the instr

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 152 of 1658 REJ09B0261-0100 7.2 Register Descriptions The following registers are re

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 153 of 1658 REJ09B0261-0100 Register Name Abbreviation Power-on Reset Manual Reset

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 154 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 10 VPN

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 155 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 8 V Undefined

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 156 of 1658 REJ09B0261-0100 7.2.4 TLB Exception Address Register (TEA) After an MMU

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 157 of 1658 REJ09B0261-0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit:000000

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 158 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 25, 24 ⎯ All

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 159 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7 ME 0 R/W

Rev.1.00 Jan. 10, 2008 Page xix of xxx REJ09B0261-0100 18.3.4 Timer Control Registers (TCRn) (n = 0 to 5) ...

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 160 of 1658 REJ09B0261-0100 Bit Bit NameInitial Value R/W Description 31 to 14 ⎯ All

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 161 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 8 ⎯ All

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 162 of 1658 REJ09B0261-0100 7.2.8 Instruction Re-Fetch Inhibit Control Register (IRM

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 163 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 R1 0 R/W

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 164 of 1658 REJ09B0261-0100 7.3 TLB Functions (TLB Compatible Mode; MMUCR.ME = 0) 7.

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 165 of 1658 REJ09B0261-0100 • SH: Share status bit When 0, pages are not shared by p

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 166 of 1658 REJ09B0261-0100 1: Cacheable When the control register area is mapped, th

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 167 of 1658 REJ09B0261-0100 7.3.2 Instruction TLB (ITLB) Configuration The ITLB is u

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 168 of 1658 REJ09B0261-0100 SR.MD?R/W?R/W?YesYesNoNoNoYesYesYesNoPR?PR?D?R/W?WWWRRR R

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 169 of 1658 REJ09B0261-0100 Figure 7.10 shows a flowchart of a memory access using th

Rev.1.00 Jan. 10, 2008 Page ii of xxx REJ09B0261-0100 1. This document is provided for reference purposes only so that Renesas customers may sele

Rev.1.00 Jan. 10, 2008 Page xx of xxx REJ09B0261-0100 19.3.26 Color Palette 4 Transparent Color Register (CP4TR) ...

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 170 of 1658 REJ09B0261-0100 7.4 TLB Functions (TLB Extended Mode; MMUCR.ME = 1) 7.4.

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 171 of 1658 REJ09B0261-0100 0001: 4-Kbyte page 0010: 8-Kbyte page 0100: 64-Kbyte page

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 172 of 1658 REJ09B0261-0100 EPR[1]: Writing in user mode EPR[0]: Execution in user mo

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 173 of 1658 REJ09B0261-0100 Virtual address Physical address311-Kbyte page10 9 0VPN O

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 174 of 1658 REJ09B0261-0100 7.4.3 Address Translation Method Figure 7.14 is a flowch

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 175 of 1658 REJ09B0261-0100 SH = 0 and (MMUCR.SV = 0 orSR.MD = 0)VPNs match,ASIDs mat

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 176 of 1658 REJ09B0261-0100 Figure 7.15 is a flowchart of memory access using the ITL

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 177 of 1658 REJ09B0261-0100 7.5 MMU Functions 7.5.1 MMU Hardware Management This LS

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 178 of 1658 REJ09B0261-0100 7.5.3 MMU Instruction (LDTLB) A TLB load instruction (LD

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 179 of 1658 REJ09B0261-0100 The operation of the LDTLB instruction is shown in figure

Rev.1.00 Jan. 10, 2008 Page xxi of xxx REJ09B0261-0100 19.4.12 Scroll Display ...

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 180 of 1658 REJ09B0261-0100 PPN[28:10]PPN[28:10]PPN[28:10]ESZ[3:0]ESZ[3:0]ESZ[3:0]SHS

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 181 of 1658 REJ09B0261-0100 7.5.5 Avoiding Synonym Problems When information on 1- o

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 182 of 1658 REJ09B0261-0100 7.6 MMU Exceptions There are seven MMU exceptions: instr

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 183 of 1658 REJ09B0261-0100 7.6.2 Instruction TLB Miss Exception An instruction TLB

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 184 of 1658 REJ09B0261-0100 3. In TLB compatible mode, execute the LDTLB instruction

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 185 of 1658 REJ09B0261-0100 (2) Software Processing (Instruction TLB Protection Viol

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 186 of 1658 REJ09B0261-0100 3. Sets exception code H'040 in the case of a read,

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 187 of 1658 REJ09B0261-0100 7.6.6 Data TLB Protection Violation Exception A data TLB

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 188 of 1658 REJ09B0261-0100 7.6.7 Initial Page Write Exception An initial page write

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 189 of 1658 REJ09B0261-0100 5. In TLB compatible mode, execute the LDTLB instruction

Rev.1.00 Jan. 10, 2008 Page xxii of xxx REJ09B0261-0100 20.3.21 MC Command FIFO (MCCF) ...

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 190 of 1658 REJ09B0261-0100 7.7 Memory-Mapped TLB Configuration To enable the ITLB a

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 191 of 1658 REJ09B0261-0100 7.7.1 ITLB Address Array The ITLB address array is alloc

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 192 of 1658 REJ09B0261-0100 7.7.2 ITLB Data Array (TLB Compatible Mode) The ITLB dat

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 193 of 1658 REJ09B0261-0100 7.7.3 ITLB Data Array (TLB Extended Mode) In TLB extende

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 194 of 1658 REJ09B0261-0100 (2) ITLB Data Array 2 The ITLB data array is allocated t

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 195 of 1658 REJ09B0261-0100 7.7.4 UTLB Address Array The UTLB address array is alloc

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 196 of 1658 REJ09B0261-0100 Address fieldData fieldVPN:V:E:D:*:Virtual page numberVal

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 197 of 1658 REJ09B0261-0100 Address fieldData fieldPPN:V:E:SZ:D:*:Physical page numbe

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 198 of 1658 REJ09B0261-0100 (2) UTLB Data Array 2 The UTLB data array is allocated t

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 199 of 1658 REJ09B0261-0100 7.8 32-Bit Address Extended Mode Setting the SE bit in P

Rev.1.00 Jan. 10, 2008 Page xxiii of xxx REJ09B0261-0100 21.3.12 Serial Port Register n (SCSPTR) ...

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 200 of 1658 REJ09B0261-0100 7.8.2 Transition to 32-Bit Address Extended Mode This LS

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 201 of 1658 REJ09B0261-0100 Legend: • VPN: Virtual page number For 16-Mbyte page: Up

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 202 of 1658 REJ09B0261-0100 • WT: Write-through bit Specifies the cache write mode.

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 203 of 1658 REJ09B0261-0100 7.8.5 Memory-Mapped PMB Configuration To enable the PMB

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 204 of 1658 REJ09B0261-0100 Address fieldData fieldVPN:V:E:Physical page numberValidi

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 205 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 30 to 8 ⎯ All

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 206 of 1658 REJ09B0261-0100 (5) CCR.CB The CB bit in CCR is invalid. Whether a cache

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 207 of 1658 REJ09B0261-0100 7.9 32-Bit Boot Function The address mode of this LSI af

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 208 of 1658 REJ09B0261-0100 C. If the MT bit in IRMCR is set to 0 (initial value) be

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 209 of 1658 REJ09B0261-0100 7.10 Usage Notes 7.10.1 Note on Using LDTLB Instruction

Rev.1.00 Jan. 10, 2008 Page xxiv of xxx REJ09B0261-0100 23.2 Input/Output Pins...

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 210 of 1658 REJ09B0261-0100 Notes: 1. An exception handling routine is an entire se

8. Caches Rev.1.00 Jan. 10, 2008 Page 211 of 1658 REJ09B0261-0100 Section 8 Caches This LSI has an on-chip 32-Kbyte instruction cache (IC) for

8. Caches Rev.1.00 Jan. 10, 2008 Page 212 of 1658 REJ09B0261-0100 This LSI has an IC way prediction scheme to reduce power consumption. In additi

8. Caches Rev.1.00 Jan. 10, 2008 Page 213 of 1658 REJ09B0261-0100 31 54 2LW032 bitsLW132 bitsLW232 bitsLW332 bitsLW432 bitsLW532 bitsLW632 bitsLW

8. Caches Rev.1.00 Jan. 10, 2008 Page 214 of 1658 REJ09B0261-0100 • Data array The data field holds 32 bytes (256 bits) of data per cache line.

8. Caches Rev.1.00 Jan. 10, 2008 Page 215 of 1658 REJ09B0261-0100 8.2 Register Descriptions The following registers are related to cache. Table

8. Caches Rev.1.00 Jan. 10, 2008 Page 216 of 1658 REJ09B0261-0100 8.2.1 Cache Control Register (CCR) CCR controls the cache operating mode, the

8. Caches Rev.1.00 Jan. 10, 2008 Page 217 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 10, 9 ⎯ All 0 R Reserved For detail

8. Caches Rev.1.00 Jan. 10, 2008 Page 218 of 1658 REJ09B0261-0100 8.2.2 Queue Address Control Register 0 (QACR0) QACR0 specifies the area onto w

8. Caches Rev.1.00 Jan. 10, 2008 Page 219 of 1658 REJ09B0261-0100 8.2.3 Queue Address Control Register 1 (QACR1) QACR1 specifies the area onto w

Rev.1.00 Jan. 10, 2008 Page xxv of xxx REJ09B0261-0100 24.4.1 Operations in MMC Mode...

8. Caches Rev.1.00 Jan. 10, 2008 Page 220 of 1658 REJ09B0261-0100 8.2.4 On-Chip Memory Control Register (RAMCR) RAMCR controls the number of way

8. Caches Rev.1.00 Jan. 10, 2008 Page 221 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 8 RP 0 R/W On-Chip Memory Protec

8. Caches Rev.1.00 Jan. 10, 2008 Page 222 of 1658 REJ09B0261-0100 8.3 Operand Cache Operation 8.3.1 Read Operation When the Operand Cache (OC)

8. Caches Rev.1.00 Jan. 10, 2008 Page 223 of 1658 REJ09B0261-0100 write-back buffer is then written back to external memory. 8.3.2 Prefetch Ope

8. Caches Rev.1.00 Jan. 10, 2008 Page 224 of 1658 REJ09B0261-0100 8.3.3 Write Operation When the Operand Cache (OC) is enabled (OCE = 1 in CCR)

8. Caches Rev.1.00 Jan. 10, 2008 Page 225 of 1658 REJ09B0261-0100 6. Cache miss (copy-back, with write-back) The tag and data field of the cache

8. Caches Rev.1.00 Jan. 10, 2008 Page 226 of 1658 REJ09B0261-0100 8.3.6 OC Two-Way Mode When the OC2W bit in RAMCR is set to 1, OC two-way mode

8. Caches Rev.1.00 Jan. 10, 2008 Page 227 of 1658 REJ09B0261-0100 8.4 Instruction Cache Operation 8.4.1 Read Operation When the IC is enabled (

8. Caches Rev.1.00 Jan. 10, 2008 Page 228 of 1658 REJ09B0261-0100 3. Cache hit The LRU bits is updated to indicate the way is the latest one. 4.

8. Caches Rev.1.00 Jan. 10, 2008 Page 229 of 1658 REJ09B0261-0100 8.5 Cache Operation Instruction 8.5.1 Coherency between Cache and External Me

Rev.1.00 Jan. 10, 2008 Page xxvi of xxx REJ09B0261-0100 26.4 Operation ...

8. Caches Rev.1.00 Jan. 10, 2008 Page 230 of 1658 REJ09B0261-0100 • FLUSH transaction When the operand cache is enabled, the FLUSH transaction c

8. Caches Rev.1.00 Jan. 10, 2008 Page 231 of 1658 REJ09B0261-0100 the dirty bit to 0. This operation is only executable in privileged mode, and a

8. Caches Rev.1.00 Jan. 10, 2008 Page 232 of 1658 REJ09B0261-0100 8.6 Memory-Mapped Cache Configuration The IC and OC can be managed by software

8. Caches Rev.1.00 Jan. 10, 2008 Page 233 of 1658 REJ09B0261-0100 In the data field, the tag is indicated by bits [31:10], and the V bit by bit [

8. Caches Rev.1.00 Jan. 10, 2008 Page 234 of 1658 REJ09B0261-0100 8.6.2 IC Data Array The IC data array is allocated to addresses H'F100 00

8. Caches Rev.1.00 Jan. 10, 2008 Page 235 of 1658 REJ09B0261-0100 32-bit data field specification. The way and entry to be accessed are specified

8. Caches Rev.1.00 Jan. 10, 2008 Page 236 of 1658 REJ09B0261-0100 Address field31 23 5432101 1 1 1 0 1 0 0 Entry AData field31 10 9 1 0VTag24 131

8. Caches Rev.1.00 Jan. 10, 2008 Page 237 of 1658 REJ09B0261-0100 Address field31 23 5432101 1 1 1 0 1 0 1 EntryData field31 0Longword data24 131

8. Caches Rev.1.00 Jan. 10, 2008 Page 238 of 1658 REJ09B0261-0100 8.7 Store Queues This LSI supports two 32-byte store queues (SQs) to perform h

8. Caches Rev.1.00 Jan. 10, 2008 Page 239 of 1658 REJ09B0261-0100 8.7.3 Transfer to External Memory Transfer from the SQs to external memory can

Rev.1.00 Jan. 10, 2008 Page xxvii of xxx REJ09B0261-0100 Section 28 General Purpose I/O Ports (GPIO)...

8. Caches Rev.1.00 Jan. 10, 2008 Page 240 of 1658 REJ09B0261-0100 Physical address bits [4:0] are always fixed at 0 since burst transfer starts a

8. Caches Rev.1.00 Jan. 10, 2008 Page 241 of 1658 REJ09B0261-0100 8.8 Notes on Using 32-Bit Address Extended Mode In 32-bit address extended mod

8. Caches Rev.1.00 Jan. 10, 2008 Page 242 of 1658 REJ09B0261-0100

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 243 of 1658 REJ09B0261-0100 Section 9 On-Chip Memory This LSI includes three types of memory modu

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 244 of 1658 REJ09B0261-0100 (2) IL Memory • Capacity The IL memory in this LSI is 8 Kbytes. • Pa

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 245 of 1658 REJ09B0261-0100 The CPU can access the P4 area in the virtual address space (when SR.MD

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 246 of 1658 REJ09B0261-0100 9.2 Register Descriptions The following registers are related to the o

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 247 of 1658 REJ09B0261-0100 9.2.1 On-Chip Memory Control Register (RAMCR) RAMCR controls the prote

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 248 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 OC2W 0 R/W OC Two-Way

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 249 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 to 0 L0SSZ Undefined R/

Rev.1.00 Jan. 10, 2008 Page xxviii of xxx REJ09B0261-0100 28.2.37 Port L Pull-Up Control Register (PLPUPR)...

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 250 of 1658 REJ09B0261-0100 9.2.3 OL memory Transfer Source Address Register 1 (LSA1) When MMUCR.A

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 251 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 to 0 L1SSZ Undefined R/

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 252 of 1658 REJ09B0261-0100 9.2.4 OL memory Transfer Destination Address Register 0 (LDA0) When MM

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 253 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 to 0 L0DSZ Undefined R/

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 254 of 1658 REJ09B0261-0100 9.2.5 OL memory Transfer Destination Address Register 1 (LDA1) When MM

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 255 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 to 0 L1DSZ Undefined R/

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 256 of 1658 REJ09B0261-0100 9.3 Operation 9.3.1 Instruction Fetch Access from the CPU (1) OL Mem

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 257 of 1658 REJ09B0261-0100 (3) U Memory Operand access from the CPU and read access from the FPU

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 258 of 1658 REJ09B0261-0100 (1) When MMU is Enabled (MMUCR.AT = 1) and RAMCR.RP = 1 An address of

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 259 of 1658 REJ09B0261-0100 When the PREF instruction is issued to the OL memory area, the physical

Rev.1.00 Jan. 10, 2008 Page xxix of xxx REJ09B0261-0100 30.3.2 Interrupt Source Register (SDINT)...

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 260 of 1658 REJ09B0261-0100 9.4 On-Chip Memory Protective Functions This LSI implements the follow

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 261 of 1658 REJ09B0261-0100 9.5 Usage Notes 9.5.1 Page Conflict In the event of simultaneous acce

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 262 of 1658 REJ09B0261-0100 (2) IL Memory In order to allocate instructions in the IL memory, writ

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 263 of 1658 REJ09B0261-0100 Section 10 Interrupt Controller (INTC) The interrupt co

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 264 of 1658 REJ09B0261-0100 Figure 10.1 shows a block diagram of the INTC. Input cont

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 265 of 1658 REJ09B0261-0100 The details of the input control circuit of figure 10.1 a

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 266 of 1658 REJ09B0261-0100 10.1.1 Interrupt Method The basic flow of exception hand

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 267 of 1658 REJ09B0261-0100 10.1.2 Interrupt Sources Table 10.1 shows an example of

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 268 of 1658 REJ09B0261-0100 Source Number of Sources (Max.) Priority INTEVT Remarks

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 269 of 1658 REJ09B0261-0100 Source Number of Sources (Max.) Priority INTEVT Remarks

Rev.1.00 Jan. 10, 2008 Page iii of xxx REJ09B0261-0100 General Precautions in the Handling of MPU/MCU Products The following usage notes are appli

Rev.1.00 Jan. 10, 2008 Page xxx of xxx REJ09B0261-0100 Appendix ...

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 270 of 1658 REJ09B0261-0100 Source Number of Sources (Max.) Priority INTEVT Remarks

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 271 of 1658 REJ09B0261-0100 BRI0, BRI1, BRI2, BRI3, BRI4, BRI5: SCIF channels 0 to

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 272 of 1658 REJ09B0261-0100 10.2 Input/Output Pins Table 10.2 shows the pin configur

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 273 of 1658 REJ09B0261-0100 10.3 Register Descriptions Table 10.3 shows the INTC reg

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 274 of 1658 REJ09B0261-0100 Name Abbreviation R/W P4 Address Area 7 Address Acces

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 275 of 1658 REJ09B0261-0100 Table 10.4 Register States in Each Operating Mode Name A

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 276 of 1658 REJ09B0261-0100 Name Abbreviation Power-on Reset by PRESET Pin/WDT/H-UDIM

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 277 of 1658 REJ09B0261-0100 10.3.1 External Interrupt Request Registers (1) Interru

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 278 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 25 NMIB 0 R/W

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 279 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 21 LVLMODE 0 R/W

1. Overview Rev.1.00 Jan. 10, 2008 Page 1 of 1658 REJ09B0261-0100 Section 1 Overview The SH7785 incorporates a DDR2-SDRAM interface, a PCI cont

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 280 of 1658 REJ09B0261-0100 (2) Interrupt Control Register 1 (ICR1) ICR1 is a 32-bit

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 281 of 1658 REJ09B0261-0100 IRQ and IRL Interrupt Requests). 2. When the IRQnS set

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 282 of 1658 REJ09B0261-0100 (3) Interrupt Priority Register (INTPRI) INTPRI is a 32-

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 283 of 1658 REJ09B0261-0100 (4) Interrupt Source Register (INTREQ) INTREQ is a 32-bi

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 284 of 1658 REJ09B0261-0100 (5) Interrupt Mask Register 0 (INTMSK0) INTMSK0 is a 32-

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 285 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 26 IM05 1 R/W Set

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 286 of 1658 REJ09B0261-0100 (6) Interrupt Mask Register 1 (INTMSK1) INTMSK1 is a 32-

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 287 of 1658 REJ09B0261-0100 (7) Interrupt Mask Register 2 (INTMSK2) INTMSK2 is a 32-

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 288 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 26 IM010 0 R/W

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 289 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 15 IM115 0 R/W

1. Overview Rev.1.00 Jan. 10, 2008 Page 2 of 1658 REJ09B0261-0100 Item Features CPU • Renesas Technology original architecture • 32-bit interna

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 290 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 2 IM102 0 R/W

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 291 of 1658 REJ09B0261-0100 (8) Interrupt Mask Clear Register 0 (INTMSKCLR0) INTMSKC

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 292 of 1658 REJ09B0261-0100 (9) Interrupt Mask Clear Register 1 (INTMSKCLR1) INTMSKC

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 293 of 1658 REJ09B0261-0100 (10) Interrupt Mask Clear Register 2 (INTMSKCLR2) INTMSK

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 294 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 23 IC007 0 R/W

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 295 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 11 IC111 0 R/W

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 296 of 1658 REJ09B0261-0100 (11) NMI Flag Control Register (NMIFCR) NMIFCR is a 32-b

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 297 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 16 NMIFL 0 R/(W

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 298 of 1658 REJ09B0261-0100 10.3.2 User Mode Interrupt Disable Function (1) User In

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 299 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 31 to 24 (Code f

1. Overview Rev.1.00 Jan. 10, 2008 Page 3 of 1658 REJ09B0261-0100 Item Features FPU • On-chip floating-point coprocessor • Supports single (32-

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 300 of 1658 REJ09B0261-0100 3. Branch to the device driver. 4. In the device driver

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 301 of 1658 REJ09B0261-0100 Table 10.5 Interrupt Request Sources and INT2PRI0 to INT

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 302 of 1658 REJ09B0261-0100 (2) Interrupt Source Register (Not affected by Mask Sett

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 303 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 21 Und

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 304 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 5 Unde

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 305 of 1658 REJ09B0261-0100 Table 10.7 Reflection time for INT2A0 and INT2A1 when In

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 306 of 1658 REJ09B0261-0100 Module Relation between Setting/Clearing Interrupt Source

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 307 of 1658 REJ09B0261-0100 (3) Interrupt Source Register (Affected by Mask States)

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 308 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 20 0

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 309 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 3 0

1. Overview Rev.1.00 Jan. 10, 2008 Page 4 of 1658 REJ09B0261-0100 Item Features Memory management unit (MMU) • 4-Gbyte address space, 256 addre

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 310 of 1658 REJ09B0261-0100 (4) Interrupt Mask Register (INT2MSKR) INT2MSKR is a 32-

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 311 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 18

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 312 of 1658 REJ09B0261-0100 (5) Interrupt Mask Clear Register (INT2MSKCR) INT2MSKCR

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 313 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 18

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 314 of 1658 REJ09B0261-0100 10.3.4 Individual On-Chip Module Interrupt Source Regist

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 315 of 1658 REJ09B0261-0100 (2) INT2B1: Detailed Interrupt Sources for the SCIF Modu

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 316 of 1658 REJ09B0261-0100 Module Bit Name Detailed Source Description SCIF 11 T

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 317 of 1658 REJ09B0261-0100 (3) INT2B2: Detailed Interrupt Sources for the DMAC Modu

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 318 of 1658 REJ09B0261-0100 (4) INT2B3: Detailed Interrupt Sources for the PCIC Modu

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 319 of 1658 REJ09B0261-0100 (5) INT2B4: Detailed Interrupt Sources for the MMCIF Mod

1. Overview Rev.1.00 Jan. 10, 2008 Page 5 of 1658 REJ09B0261-0100 Item Features URAM • 128-Kbyte large-capacity memory • Three independent rea

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 320 of 1658 REJ09B0261-0100 (7) INT2B6: Detailed Interrupt Sources for the GPIO Modu

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 321 of 1658 REJ09B0261-0100 (8) INT2B7: Detailed Interrupt Sources for the GDTA Modu

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 322 of 1658 REJ09B0261-0100 10.3.5 GPIO Interrupt Set Register (INT2GPIC) INT2GPIC e

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 323 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Function Description 18 POR

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 324 of 1658 REJ09B0261-0100 10.4 Interrupt Sources There are four types of interrupt

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 325 of 1658 REJ09B0261-0100 (2) Dependence on ICR0.LVLMODE Setting For the IRQ inter

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 326 of 1658 REJ09B0261-0100 Priorityencoder InterruptrequestsSH7785IRQ/IRL3 to IRQ/

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 327 of 1658 REJ09B0261-0100 The priority of IRL interrupts should be retained from wh

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 328 of 1658 REJ09B0261-0100 An on-chip peripheral module interrupt source flag or an

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 329 of 1658 REJ09B0261-0100 An interrupt request is masked if priority level H'0

1. Overview Rev.1.00 Jan. 10, 2008 Page 6 of 1658 REJ09B0261-0100 Item Features Local bus state controller (LBSC) • A dedicated Local-bus inter

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 330 of 1658 REJ09B0261-0100 Table 10.13 Interrupt Exception Handling and Priority In

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 331 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clea

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 332 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clea

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 333 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clea

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 334 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clea

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 335 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clea

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 336 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clea

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 337 of 1658 REJ09B0261-0100 10.5 Operation 10.5.1 Interrupt Sequence The sequence o

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 338 of 1658 REJ09B0261-0100 Program execution state Interruptgenerated?ICR0.MAI = 1?S

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 339 of 1658 REJ09B0261-0100 10.5.2 Multiple Interrupts To handle multiple interrupts

1. Overview Rev.1.00 Jan. 10, 2008 Page 7 of 1658 REJ09B0261-0100 Item Features DDR2-SDRAM bus controller (DBSC) • A dedicated DDR2-SDRAM bus in

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 340 of 1658 REJ09B0261-0100 10.6 Interrupt Response Time Table 10.14 shows response

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 341 of 1658 REJ09B0261-0100 Table 10.15 shows response time. The response time is fro

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 342 of 1658 REJ09B0261-0100 Table 10.16 shows response time. The response time is the

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 343 of 1658 REJ09B0261-0100 10.7 Usage Notes 10.7.1 Example of Handing Routine of I

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 344 of 1658 REJ09B0261-0100 10.7.2 Notes on Setting IRQ/IRL[7:0] Pin Function When t

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 345 of 1658 REJ09B0261-0100 10.7.3 Clearing IRQ and IRL Interrupt Requests To clear

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 346 of 1658 REJ09B0261-0100

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 347 of 1658 REJ09B0261-0100 Section 11 Local Bus State Controller (LBSC) The

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 348 of 1658 REJ09B0261-0100 • MPX interface ⎯ Address/data multiplexing Conne

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 349 of 1658 REJ09B0261-0100 Figure 11.1 shows a block diagram of the LBSC. Bus

1. Overview Rev.1.00 Jan. 10, 2008 Page 8 of 1658 REJ09B0261-0100 Item Features PCI bus controller (PCIC) • PCI bus controller (supports a subse

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 350 of 1658 REJ09B0261-0100 11.2 Input/Output Pins Table 11.1 shows the LBSC p

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 351 of 1658 REJ09B0261-0100 Pin Name Function I/O Description WE0/REG Data

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 352 of 1658 REJ09B0261-0100 Pin Name Function I/O Description BACK Bus Requ

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 353 of 1658 REJ09B0261-0100 Pin Name Function I/O Description MODE11, MODE12

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 354 of 1658 REJ09B0261-0100 11.3 Overview of Areas 11.3.1 Space Divisions The

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 355 of 1658 REJ09B0261-0100 Table 11.2 LBSC External Memory Space Map Area Ext

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 356 of 1658 REJ09B0261-0100 Area External addresses Size Connectable Memory Spe

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 357 of 1658 REJ09B0261-0100 11.3.2 Memory Bus Width The memory bus width of th

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 358 of 1658 REJ09B0261-0100 11.3.3 PCMCIA Support This LSI supports the PCMCIA

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 359 of 1658 REJ09B0261-0100 Table 11.4 PCMCIA Support Interface IC Memory Ca

1. Overview Rev.1.00 Jan. 10, 2008 Page 9 of 1658 REJ09B0261-0100 Item Features Watchdog timer (WDT) • Number of channels: One • Single-channe

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 360 of 1658 REJ09B0261-0100 IC Memory Card Interface I/O Card Interface Pi

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 361 of 1658 REJ09B0261-0100 IC Memory Card Interface I/O Card Interface Pi

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 362 of 1658 REJ09B0261-0100 11.4 Register Descriptions Table 11.5 shows regist

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 363 of 1658 REJ09B0261-0100 Table 11.5 Register Configuration (2) Register Nam

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 364 of 1658 REJ09B0261-0100 11.4.1 Memory Address Map Select Register (MMSELR)

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 365 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 366 of 1658 REJ09B0261-0100 Example: ------------------------------------------

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 367 of 1658 REJ09B0261-0100 11.4.2 Bus Control Register (BCR) BCR is a 32-bit

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 368 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 26 DPU

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 369 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 19, 18

Rev.1.00 Jan. 10, 2008 Page iv of xxx REJ09B0261-0100

1. Overview Rev.1.00 Jan. 10, 2008 Page 10 of 1658 REJ09B0261-0100 Item Features Display unit (DU) • Display plane ⎯ 6 planes (a maximum number

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 370 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 to 0

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 371 of 1658 REJ09B0261-0100 11.4.3 CSn Bus Control Register (CSnBCR) CSnBCR ar

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 372 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 30 to 2

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 373 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 23 ⎯ 0

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 374 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 ⎯ 0

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 375 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 9, 8 SZ

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 376 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 to 4

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 377 of 1658 REJ09B0261-0100 11.4.4 CSn Wait Control Register (CSnWCR) CSnWCR (

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 378 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 27 ⎯ 0

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 379 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 19 ⎯ 0

1. Overview Rev.1.00 Jan. 10, 2008 Page 11 of 1658 REJ09B0261-0100 Item Features Synchronized serial I/O with FIFO (SIOF) • Number of channels:

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 380 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 11 ⎯ 0

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 381 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 to 0

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 382 of 1658 REJ09B0261-0100 11.4.5 CSn PCMCIA Control Register (CSnPCR) CSnPCR

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 383 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 27 ⎯ 0

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 384 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 19 to 1

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 385 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 14 to 1

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 386 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 to 4

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 387 of 1658 REJ09B0261-0100 11.5 Operation 11.5.1 Endian/Access Size and Data

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 388 of 1658 REJ09B0261-0100 Table 11.6 64-Bit External Device/Big Endian Acces

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 389 of 1658 REJ09B0261-0100 Table 11.7 64-Bit External Device/Big Endian Acces

1. Overview Rev.1.00 Jan. 10, 2008 Page 12 of 1658 REJ09B0261-0100 Item Features Serial sound interface (SSI) • Number of channels: Two (max.) •

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 390 of 1658 REJ09B0261-0100 Table 11.8 32-Bit External Device/Big-Endian Acces

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 391 of 1658 REJ09B0261-0100 Table 11.9 16-Bit External Device/Big-Endian Acces

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 392 of 1658 REJ09B0261-0100 Table 11.10 8-Bit External Device/Big-Endian Acces

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 393 of 1658 REJ09B0261-0100 Table 11.11 64-Bit External Device/Little Endian A

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 394 of 1658 REJ09B0261-0100 Table 11.12 64-Bit External Device/Little Endian A

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 395 of 1658 REJ09B0261-0100 Table 11.13 32-Bit External Device/Little-Endian A

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 396 of 1658 REJ09B0261-0100 Table 11.14 16-Bit External Device/Little-Endian A

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 397 of 1658 REJ09B0261-0100 Table 11.15 8-Bit External Device/Little-Endian Ac

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 398 of 1658 REJ09B0261-0100 11.5.2 Areas (1) Area 0 Area 0 is an area where b

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 399 of 1658 REJ09B0261-0100 For the number of bus cycles, 0 to 25 wait cycles t

1. Overview Rev.1.00 Jan. 10, 2008 Page 13 of 1658 REJ09B0261-0100 1.2 Block Diagram A block diagram of the SH7785 is given as figure 1.1. ROM

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 400 of 1658 REJ09B0261-0100 (4) Area 3 Area 3 is an area where bits 28 to 26 i

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 401 of 1658 REJ09B0261-0100 For the number of bus cycles, 0 to 25 wait cycles i

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 402 of 1658 REJ09B0261-0100 CS5PCR. In addition, the number of wait cycles can

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 403 of 1658 REJ09B0261-0100 11.5.3 SRAM interface (1) Basic Timing The strobe

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 404 of 1658 REJ09B0261-0100 T1CLKOUTA25 to A0CSnR/WRDD31 to D0(In reading)WEnD3

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 405 of 1658 REJ09B0261-0100 Figures 11.6 to 11.8 show examples of connections t

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 406 of 1658 REJ09B0261-0100 A16A0CSOEI/O7I/O0WEA17A1CSnRDD15D8WE1D7D0WE0SH77851

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 407 of 1658 REJ09B0261-0100 A16A0CSnRDD7D0WE0SH7785128K × 8 bitsSRAMA16A0CSOEI/

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 408 of 1658 REJ09B0261-0100 T1CLKOUTA25 to A0CSnR/WRDD31 to D0(In reading)WEnD3

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 409 of 1658 REJ09B0261-0100 When software wait insertion is specified by CSnWCR

1. Overview Rev.1.00 Jan. 10, 2008 Page 14 of 1658 REJ09B0261-0100 1.3 Pin Arrangement Table Table 1.2 Pin Function No. Pin Name I/O Functio

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 410 of 1658 REJ09B0261-0100 (3) Read-Strobe/Write-Strobe Timing When the SRAM

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 411 of 1658 REJ09B0261-0100 TAS1CLKOUTA25-A0CSnR/WRDD31-D0T1 TS1 Tw Tw Tw T2Tw

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 412 of 1658 REJ09B0261-0100 11.5.4 Burst ROM Interface When the TYPE bit in CS

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 413 of 1658 REJ09B0261-0100 T1 TB1 TB2 TB1 TB2 TB1TB2 T2CLKOUTA25 to A5A4 to A0

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 414 of 1658 REJ09B0261-0100 T1 Twe TB2 TB1 Tw TB2 TwTw TB1 TB2 Tw T2TB1CLKOUTA2

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 415 of 1658 REJ09B0261-0100 *2TAS1 TS1 TB2 TB1 TB2 TB1 TB1T1 TB2 T2 TAH1TH1CLKO

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 416 of 1658 REJ09B0261-0100 11.5.5 PCMCIA Interface By setting the TYPE bits i

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 417 of 1658 REJ09B0261-0100 complement mode. To access the Device Control Regis

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 418 of 1658 REJ09B0261-0100 Table 11.16 Relationship between Address and CE wh

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 419 of 1658 REJ09B0261-0100 Bus (Bits) Read/ Write Access (bits)*1 Odd/ Even IO

1. Overview Rev.1.00 Jan. 10, 2008 Page 15 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 55 MA10 O DDR add

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 420 of 1658 REJ09B0261-0100 GA25 to A0D15 to D0PC card (memory I/O)CD1, CD2CE1G

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 421 of 1658 REJ09B0261-0100 (1) Memory Card Interface Basic Timing Figure 11.1

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 422 of 1658 REJ09B0261-0100 CLKOUTTpcm0A25 to A0R/WCExxREGRD(In reading)D15 to

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 423 of 1658 REJ09B0261-0100 (2) I/O Card Interface Timing Figures 11.19 and 11

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 424 of 1658 REJ09B0261-0100 CLKOUTTpci1 Tpci2A25 to A0R/WCExxICIORD(In reading)

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 425 of 1658 REJ09B0261-0100 CLKOUTA25 to A0R/WCExxICIORD(In reading)ICIOWR(In w

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 426 of 1658 REJ09B0261-0100 TpciTpci0 Tpci1w Tpci2 Tpci2w Tpci0 TpciTpci2Tpci1w

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 427 of 1658 REJ09B0261-0100 11.5.6 MPX Interface When both the MODE 7 pin is s

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 428 of 1658 REJ09B0261-0100 CLKOUTCSnBSRDR/WD31 to D0RDYSH7785MPX deviceCLKCSBS

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 429 of 1658 REJ09B0261-0100 Tm1 Tm1CLKOUTRD/FRAMECSnR/WD63 to D0BSTmd1wTmd1RDYD

1. Overview Rev.1.00 Jan. 10, 2008 Page 16 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 119 A12 O Local b

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 430 of 1658 REJ09B0261-0100 Tm1CLKOUTARD/FRAMECSnR/WD63 to D0BSTmd1w Tmd1wTmd1R

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 431 of 1658 REJ09B0261-0100 Tm1CLKOUTARD/FRAMECSnR/WD63 to D0BSTmd1RDYDACKnD0In

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 432 of 1658 REJ09B0261-0100 Tm1CLKOUTARD/FRAMECSnR/WD63 to D0BSTmd1w Tmd1wTmd1R

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 433 of 1658 REJ09B0261-0100 Tm1CLKOUTRD/FRAMECSnR/WD63 to D0BSTmd1w Tmd1Tmd2 Tm

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 434 of 1658 REJ09B0261-0100 Tm1CLKOUTARD/FRAMECSnR/WD63 to D0BSTmd1w Tmd1 Tmd2w

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 435 of 1658 REJ09B0261-0100 Tm1CLKOUTARD/FRAMECSnR/WD63 to D0BSTmd1 Tmd2 Tmd3 T

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 436 of 1658 REJ09B0261-0100 D2D1Tm1CLKOUTARD/FRAMECSnR/WD63 to D0BSTmd1w Tmd1Tm

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 437 of 1658 REJ09B0261-0100 Tm1CLKOUTRD/FRAMECSnR/WD31 to D0BSTmd1w Tmd1Tmd2 Tm

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 438 of 1658 REJ09B0261-0100 Tm1CLKOUTARD/FRAMECSnR/WD31 to D0BSTmd1w Tmd1 Tmd2w

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 439 of 1658 REJ09B0261-0100 Tm1CLKOUTARD/FRAMECSnR/WD31 to D0BSTmd1 Tmd2 Tmd3 T

1. Overview Rev.1.00 Jan. 10, 2008 Page 17 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 155 D37/AD5/DR5 IO/

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 440 of 1658 REJ09B0261-0100 D3D2Tm1CLKOUTARD/FRAMECSnR/WD31 to D0BSTmd1w Tmd1Tm

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 441 of 1658 REJ09B0261-0100 11.5.7 Byte Control SRAM Interface The byte contro

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 442 of 1658 REJ09B0261-0100 A18 to A3CSnRDR/WSH778564K × 16 bitsSRAMD47 to D32W

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 443 of 1658 REJ09B0261-0100 T1 T2CLKOUTA25 to A0CSnR/WRDD31 to D0(In reading)BS

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 444 of 1658 REJ09B0261-0100 TAS1CLKOUTA25-A0CSnR/WWEn(In reading)(In writing)D6

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 445 of 1658 REJ09B0261-0100 T1 Tw Twe T2CLKOUTA25 to A0CSnR/WRDD31 to D0(In rea

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 446 of 1658 REJ09B0261-0100 11.5.8 Wait Cycles between Access Cycles When the

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 447 of 1658 REJ09B0261-0100 T1CLKOUTCSmCSnA25 to A0BSR/WRDD31 to D0T2 Twait T1

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 448 of 1658 REJ09B0261-0100 11.5.9 Bus Arbitration This LSI is provided with a

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 449 of 1658 REJ09B0261-0100 Asserted for 2 cycles or moreMaster-mode device acc

1. Overview Rev.1.00 Jan. 10, 2008 Page 18 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 181 D63/AD31 IO/IO

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 450 of 1658 REJ09B0261-0100 11.5.10 Master Mode The processor in master mode h

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 451 of 1658 REJ09B0261-0100 11.5.11 Slave Mode In slave mode, usually, the bus

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 452 of 1658 REJ09B0261-0100 11.5.14 Mode Pin Settings and General Input Output

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 453 of 1658 REJ09B0261-0100 Table 11.19 Register Settings for Divided-Up DACKn

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 454 of 1658 REJ09B0261-0100 Table 11.20 Register Settings for Divided-Up DACKn

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 455 of 1658 REJ09B0261-0100 Table 11.21 Register Settings for Divided-Up DACKn

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 456 of 1658 REJ09B0261-0100 Table 11.22 Register Settings for Divided-Up DACKn

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 457 of 1658 REJ09B0261-0100 Section 12 DDR2-SDRAM Interface (DBSC2) The DDR2-SDRAM

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 458 of 1658 REJ09B0261-0100 ⎯ DDR2-SDRAM data bus width: 16 bits • One 256 Mbits (

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 459 of 1658 REJ09B0261-0100 Figure 12.1 shows a block diagram of the DBSC2. BUS IFRe

1. Overview Rev.1.00 Jan. 10, 2008 Page 19 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 217 BREQ/BSACK I

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 460 of 1658 REJ09B0261-0100 12.2 Input/Output Pins Table 12.1 shows the pin configu

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 461 of 1658 REJ09B0261-0100 The frequency of the SDRAM operation clocks MCK0, MCK0,

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 462 of 1658 REJ09B0261-0100 Table 12.2 An Example of DDR2-SDRAM Connection (When F

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 463 of 1658 REJ09B0261-0100 3. SDRAM pins should be connected as shown below. Mem

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 464 of 1658 REJ09B0261-0100 5. SDRAM pins should be connected as shown below. Mem

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 465 of 1658 REJ09B0261-0100 12.3 Data Alignment The DBSC2 accesses DDR2-SDRAM with

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 466 of 1658 REJ09B0261-0100 MCK0,MCK1MA[14:11]MA[9:0]MBA[2:0]MCKEMCSMRASMCASMWEMA[10

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 467 of 1658 REJ09B0261-0100 Table 12.3 Positions of Valid Data for Access with Burs

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 468 of 1658 REJ09B0261-0100 Table 12.4 Positions of Valid Data for Access with Burs

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 469 of 1658 REJ09B0261-0100 (2) Big Endian First Access Second Access Third Acces

Rev.1.00 Jan. 10, 2008 Page v of xxx REJ09B0261-0100 Preface This LSI is a RISC (Reduced Instruction Set Computer) microcomputer which includes a

1. Overview Rev.1.00 Jan. 10, 2008 Page 20 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 249 SIOF_SCK/ HAC0_B

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 470 of 1658 REJ09B0261-0100 Table 12.5 Data Alignment for Access in Little Endian w

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 471 of 1658 REJ09B0261-0100 Access Size Address MDQ31 to MDQ24 MDQ23 to MDQ16 MDQ15

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 472 of 1658 REJ09B0261-0100 Access Size Address MDQ31 to MDQ24 MDQ23 to MDQ16 MDQ15

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 473 of 1658 REJ09B0261-0100 Table 12.7 Data Alignment for Access in Little Endian w

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 474 of 1658 REJ09B0261-0100 Access Size Address MDQ15 to MDQ8 MDQ7 to MDQ0 Longwo

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 475 of 1658 REJ09B0261-0100 Table 12.8 Data Alignment for Access in Big Endian when

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 476 of 1658 REJ09B0261-0100 Access Size Address MDQ15 to MDQ8 MDQ7 to MDQ0 Longwo

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 477 of 1658 REJ09B0261-0100 When the external bus width is set to 16 bitsAddress 16n

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 478 of 1658 REJ09B0261-0100 When the external bus width is set to 32 bitsAddress 16n

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 479 of 1658 REJ09B0261-0100 12.4 Register Descriptions Table 12.9 shows the DBSC2 r

1. Overview Rev.1.00 Jan. 10, 2008 Page 21 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 269 MODE11/ SCIF4_SC

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 480 of 1658 REJ09B0261-0100 Table 12.9 DBSC2 Register Configuration Register Name

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 481 of 1658 REJ09B0261-0100 Table 12.10 Register Status in each Processing Mode Pow

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 482 of 1658 REJ09B0261-0100 12.4.1 DBSC2 Status Register (DBSTATE) The DBSC2 status

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 483 of 1658 REJ09B0261-0100 12.4.2 SDRAM Operation Enable Register (DBEN) The SDRAM

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 484 of 1658 REJ09B0261-0100 12.4.3 SDRAM Command Control Register (DBCMDCNT) The SD

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 485 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0 CMD2

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 486 of 1658 REJ09B0261-0100 12.4.4 SDRAM Configuration Setting Register (DBCONF) Th

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 487 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 to 10 ⎯

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 488 of 1658 REJ09B0261-0100 12.4.5 SDRAM Timing Register 0 (DBTR0) The SDRAM timing

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 489 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 23 to 20 ⎯

1. Overview Rev.1.00 Jan. 10, 2008 Page 22 of 1658 REJ09B0261-0100 1.4 Pin Arrangement Package: 436-pin FC-BGA, 19 mm x 19 mm, ball pitch: 0.8 m

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 490 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 14 to 8 TRFC

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 491 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0 TRCD2

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 492 of 1658 REJ09B0261-0100 12.4.6 SDRAM Timing Register 1 (DBTR1) The SDRAM timing

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 493 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 to 11 ⎯

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 494 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0 TWR2

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 495 of 1658 REJ09B0261-0100 12.4.7 SDRAM Timing Register 2 (DBTR2) The SDRAM timing

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 496 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 20 to 16 TRC

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 497 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 11 to 8 RDWR

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 498 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 to 0 WRRD3

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 499 of 1658 REJ09B0261-0100 12.4.8 SDRAM Refresh Control Register 0 (DBRFCNT0) The

1. Overview Rev.1.00 Jan. 10, 2008 Page 23 of 1658 REJ09B0261-0100 1234567891011121314151617181920212212345678910111213141516171819202122VSSA25SC

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 500 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 0 SRFEN 0

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 501 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 12 to 0 TREF

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 502 of 1658 REJ09B0261-0100 12.4.10 SDRAM Refresh Control Register 2 (DBRFCNT2) The

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 503 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 to 8 ⎯ A

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 504 of 1658 REJ09B0261-0100 12.4.11 SDRAM Refresh Status Register (DBRFSTS) The SDR

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 505 of 1658 REJ09B0261-0100 12.4.12 DDRPAD Frequency Setting Register (DBFREQ) The

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 506 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0 FREQ2

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 507 of 1658 REJ09B0261-0100 12.4.13 DDRPAD DIC, ODT, OCD Setting Register (DBDICODT

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 508 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 18 DIC_DQ 0

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 509 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 10 ODT_ EARLY

1. Overview Rev.1.00 Jan. 10, 2008 Page 24 of 1658 REJ09B0261-0100 1.5 Physical Memory Address Map The SH7785 supports 32-bit virtual address sp

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 510 of 1658 REJ09B0261-0100 12.4.14 SDRAM Mode Setting Register (DBMRCNT) The SDRAM

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 511 of 1658 REJ09B0261-0100 By writing to this register, the DDR2-SDRAM address and

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 512 of 1658 REJ09B0261-0100 12.5 DBSC2 Operation 12.5.1 Supported SDRAM Commands T

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 513 of 1658 REJ09B0261-0100 12.5.2 SDRAM Command Issue (1) Basic Access The DBSC2

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 514 of 1658 REJ09B0261-0100 16-bit external busRead (16 bytes)Read (1, 2, 4, 8, or 1

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 515 of 1658 REJ09B0261-0100 command to be issued at time 2 from the following reques

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 516 of 1658 REJ09B0261-0100 12.5.3 Initialization Sequence The following shows an e

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 517 of 1658 REJ09B0261-0100 10. Writing to DBMRCNT issues the MRS command to the SDR

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 518 of 1658 REJ09B0261-0100 Because access is disabled in self-refresh mode, any att

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 519 of 1658 REJ09B0261-0100 1. Check to make sure the DBSC2 is not being accessed.

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 25 of 1658 REJ09B0261-0100 Section 2 Programming Model The programming model of this LSI is ex

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 520 of 1658 REJ09B0261-0100 12.5.5 Auto-Refresh Operation When the auto-refresh en

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 521 of 1658 REJ09B0261-0100 LV1THLV0TH0TimeRefresh counter valueMax. value(Average r

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 522 of 1658 REJ09B0261-0100 Table 12.12 Relation between SDRAM Address Pins and Log

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 523 of 1658 REJ09B0261-0100 Table 12.13 Relation between SDRAM Address Pins and Log

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 524 of 1658 REJ09B0261-0100 Table 12.14 Relation between SDRAM Address Pins and Log

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 525 of 1658 REJ09B0261-0100 Table 12.15 Relation between SDRAM Address Pins and Log

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 526 of 1658 REJ09B0261-0100 Table 12.16 Relation between SDRAM Address Pins and Log

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 527 of 1658 REJ09B0261-0100 Table 12.17 Relation between SDRAM Address Pins and Log

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 528 of 1658 REJ09B0261-0100 Table 12.18 Relation between SDRAM Address Pins and Log

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 529 of 1658 REJ09B0261-0100 Table 12.19 Relation between SDRAM Address Pins and Log

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 26 of 1658 REJ09B0261-0100 2.2 Register Descriptions 2.2.1 Privileged Mode and Banks (1) Proc

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 530 of 1658 REJ09B0261-0100 12.5.7 Regarding SDRAM Access and Timing Constraints In

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 531 of 1658 REJ09B0261-0100 MCK0,MCK1MA[14:11]MA[9:0]MBA[2:0]MCKEMCSMRASMCASMWEMA[10

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 532 of 1658 REJ09B0261-0100 MCK0,MCK1MA[14:11 ]MA[9:0]MBA[2:0]MCKEMCSMRASMCASMWEMA[1

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 533 of 1658 REJ09B0261-0100 MCK0,MCK1MA[14:11]MA[9:0]MBA[2:0]MCKEMCSMRASMCASMWEMA[10

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 534 of 1658 REJ09B0261-0100 MCK0,MCK1MA[14:11]MA[9:0]MBA[2:0]MCKEMCSMRASMCASMWEMA[10

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 535 of 1658 REJ09B0261-0100 MCK0,MCK1MA[14:11]MA[9:0]MBA[2:0]MCKEMCSMRASMCASMWEMA[10

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 536 of 1658 REJ09B0261-0100 example is shown in section 12.5.11, Method for Securing

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 537 of 1658 REJ09B0261-0100 command, the constraint tRCD between the ACT command and

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 538 of 1658 REJ09B0261-0100 MCK0, MCK1MA[14:11]MA[9:0]MBA[2:0]MCKEMCSMRASMCASMWEMA[1

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 539 of 1658 REJ09B0261-0100 MCK0,MCK1MA[14:11]MA[9:0]MBA[2:0]MCKEMCSMRASMCASMWEMA[10

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 27 of 1658 REJ09B0261-0100 (DBR), which can only be accessed in privileged mode. Some bits of th

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 540 of 1658 REJ09B0261-0100 MCK0,MCK1MA[14:11]MA[9:0]MBA[2:0]MCKEMCSMRASMCASMWEMA[10

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 541 of 1658 REJ09B0261-0100 MCK0,MCK1MA[14:11]MA[9:0]MBA[2:0]MCKEMCSMRASMCASMWEMA[10

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 542 of 1658 REJ09B0261-0100 MCK0,MCK1MA[14:11]MA[9:0]MBA[2:0]MCKEMCSMRASMCASMWEMA[10

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 543 of 1658 REJ09B0261-0100 MCK0,MCK1MA[14:11] MA[9:0]MBA[2:0]MCKEMCSMRASMCASMWEMA[1

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 544 of 1658 REJ09B0261-0100 12.5.8 Important Information Regarding Use of 8-Bank DD

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 545 of 1658 REJ09B0261-0100 writeMCKCommandDataMCKEMODTTerminatingresistorin SDRAMAs

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 546 of 1658 REJ09B0261-0100 writeMCKCommandDataMCKEMODTTerminatingresistorin SDRAMre

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 547 of 1658 REJ09B0261-0100 This LSIMCKEMBKPRSTIO cellInternalCKEDBSC2Externaldevice

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 548 of 1658 REJ09B0261-0100 MCKE to high level, upon power-on reset the data within

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 549 of 1658 REJ09B0261-0100 5. The SDRAM configuration setting register (DBCONF), S

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 28 of 1658 REJ09B0261-0100 Table 2.1 Initial Register Values Type Registers Initial Value* Gen

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 550 of 1658 REJ09B0261-0100 12.5.13 Regarding MCKE Signal Operation The MCKE signal

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 551 of 1658 REJ09B0261-0100 Section 13 PCI Controller (PCIC) The PCI controller (PCIC) co

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 552 of 1658 REJ09B0261-0100 • Cache snoop functions are supported when the PCIC is a targe

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 553 of 1658 REJ09B0261-0100 Figure 13.1 shows a block diagram of the PCIC. PCI busPCIC modu

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 554 of 1658 REJ09B0261-0100 13.2 Input/Output Pins Table 13.1 shows the pin configuration

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 555 of 1658 REJ09B0261-0100 Signal Name PCI Standard Signal I/O Description LOCK/ODDF LOCK

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 556 of 1658 REJ09B0261-0100 Signal Name PCI Standard Signal I/O Description MODE12 MODE11 —

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 557 of 1658 REJ09B0261-0100 13.3 Register Descriptions Table 13.2 shows a list of PCIC reg

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 558 of 1658 REJ09B0261-0100 Name Abbreviation SH*1 R/W PCI*2 R/W P4 address Area 7 addres

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 559 of 1658 REJ09B0261-0100 Name Abbreviation SH*1 R/W PCI*2 R/W P4 address Area 7 addressS

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 29 of 1658 REJ09B0261-0100 31 0R0_BANK0*1,*2R1_BANK0*2R2_BANK0*2R3_BANK0*2R4_BANK0*2R5_BANK0*2R6

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 560 of 1658 REJ09B0261-0100 Table 13.3 Register States in Each Processing Mode Name Abbrev

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 561 of 1658 REJ09B0261-0100 Name Abbreviation Power-On Reset Manual Reset Sleep Mode PCI po

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 562 of 1658 REJ09B0261-0100 13.3.1 PCIC Enable Control Register (PCIECR) PCIECR is a regis

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 563 of 1658 REJ09B0261-0100 13.3.2 Configuration Registers The configuration registers def

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 564 of 1658 REJ09B0261-0100 (3) PCI Command Register (PCICMD) PCICMD controls the basic fu

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 565 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 PER 0 SH: R/W PCI:

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 566 of 1658 REJ09B0261-0100 (4) PCI Status Register (PCISTATUS) PCISTATUS is used to recor

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 567 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 12 RTA 0 SH: R/WC

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 568 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 ⎯ 0 SH: R/W PCI:

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 569 of 1658 REJ09B0261-0100 (6) PCI Program Interface Register (PCIPIF) This field is the

Rev.1.00 Jan. 10, 2008 Page vi of xxx REJ09B0261-0100 Abbreviations ALU Arithmetic Logic Unit ASID Address Space Identifier BGA Ball Grid Array CM

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 30 of 1658 REJ09B0261-0100 2.2.2 General Registers Figure 2.3 shows the relationship between th

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 570 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 0 OMP 0 SH: R/W PCI

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 571 of 1658 REJ09B0261-0100 (8) PCI Base Class Code Register (PCIBCC) This field defines t

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 572 of 1658 REJ09B0261-0100 (10) PCI Latency Timer Register (PCILTM) 0123456700000000LTMR/

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 573 of 1658 REJ09B0261-0100 (12) PCI BIST Register (PCIBIST) RRRRRRRRPCI R/W:0123456700000

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 574 of 1658 REJ09B0261-0100 (13) PCI I/O Base Address Register (PCIIBAR) This register is

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 575 of 1658 REJ09B0261-0100 (14) PCI Memory Base Address Register 0 (PCIMBAR0) This regist

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 576 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 19 to 4 MBA2 H&ap

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 577 of 1658 REJ09B0261-0100 (15) PCI Memory Base Address Register 1 (PCIMBAR1) This regist

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 578 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 19 to 4 MBA2 H&ap

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 579 of 1658 REJ09B0261-0100 (16) PCI Subsystem Vender ID Register (PCISVID) See the descri

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 31 of 1658 REJ09B0261-0100 Note on Programming: As the user's R0 to R7 are assigned to R0_

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 580 of 1658 REJ09B0261-0100 (18) PCI Capability Pointer Register (PCICP) This register is

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 581 of 1658 REJ09B0261-0100 (20) PCI Interrupt Pin Register (PCIINTPIN) 0123456710000000IN

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 582 of 1658 REJ09B0261-0100 (22) Maximum Latency Register (PCIMAXLAT) This register is not

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 583 of 1658 REJ09B0261-0100 (24) PCI Next Item Pointer Register (PCINIP) PCINIP indicates

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 584 of 1658 REJ09B0261-0100 (25) PCI Power Management Register (PCIPMC) PCIPMC is a 16-bit

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 585 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 8 to 6 ⎯ All 0 S

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 586 of 1658 REJ09B0261-0100 (26) PCI Power Management Control/Status Register (PCIPMCSR) T

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 587 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 1, 0 PS 00 SH: R

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 588 of 1658 REJ09B0261-0100 (27) PCIPMCSR Bridge Support Extension Register (PCIPMCSRBSE)

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 589 of 1658 REJ09B0261-0100 (28) PCI Power Consumption/Radiation Register (PCIPCDD) The da

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 32 of 1658 REJ09B0261-0100 7. Single-precision floating-point extended register matrix, XMTRX:

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 590 of 1658 REJ09B0261-0100 13.3.3 PCI Local Registers (1) PCI Control Register (PCICR) P

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 591 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 10 FTO 0 SH: R/W

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 592 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 IOCS 0 SH: R/W P

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 593 of 1658 REJ09B0261-0100 (2) PCI Local Space Register 0 (PCILSR0) See section 13.4.4 (1

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 594 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 19 to 1 ⎯ All 0

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 595 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 28 to 20 LSR 0 00

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 596 of 1658 REJ09B0261-0100 (4) PCI Local Address Register 0 (PCILAR0) See section 13.4.3

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 597 of 1658 REJ09B0261-0100 (5) PCI Local Address Register 1 (PCILAR1) See section 13.4.3

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 598 of 1658 REJ09B0261-0100 (6) PCI Interrupt Register (PCIIR) PCIIR records interrupt sou

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 599 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 9 TMTOI 0 SH: R/WC

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 33 of 1658 REJ09B0261-0100 2.2.4 Control Registers (1) Status Register (SR) 31 30 29 28 27 26

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 600 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 SDI 0 SH: R/WC PC

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 601 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 TADIM 0 SH: R/WC

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 602 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 0 MRDPEI 0 SH: R/WC

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 603 of 1658 REJ09B0261-0100 (7) PCI Interrupt Mask Register (PCIIMR) This register is the

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 604 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 SDIM 0 SH: R/W PC

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 605 of 1658 REJ09B0261-0100 (8) PCI Error Address Information Register (PCIAIR) This regi

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 606 of 1658 REJ09B0261-0100 (9) PCI Error Command Information Register (PCICIR) This regis

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 607 of 1658 REJ09B0261-0100 (10) PCI Arbiter Interrupt Register (PCIAINT) In host mode, th

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 608 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 11 MBTOI 0 SH: R/WC

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 609 of 1658 REJ09B0261-0100 (11) PCI Arbiter Interrupt Mask Register (PCIAINTM) This regis

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 34 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 27 to 16 — All 0 R Re

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 610 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 MAIM 0 SH: R/WC P

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 611 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 5 ⎯ All 0

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 612 of 1658 REJ09B0261-0100 (13) PCI PIO Address Register (PCIPAR) Setting this register g

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 613 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 to 11 DN xxxxx

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 614 of 1658 REJ09B0261-0100 (14) PCI Power Management Interrupt Register (PCIPINT) This re

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 615 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 0 PMD0 0 SH: R/WCPC

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 616 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 1 PMD1M 0 SH: R/W P

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 617 of 1658 REJ09B0261-0100 (17) PCI Memory Bank Mask Register 0 (PCIMBMR0) This register

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 618 of 1658 REJ09B0261-0100 (18) PCI Memory Bank Register 1 (PCIMBR1) This register specif

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 619 of 1658 REJ09B0261-0100 (19) PCI Memory Bank Mask Register 1 (PCIMBMR1) This register

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 35 of 1658 REJ09B0261-0100 (2) Saved Status Register (SSR) (32 bits, Privileged Mode, Initial V

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 620 of 1658 REJ09B0261-0100 (20) PCI Memory Bank Register 2 (PCIMBR2) This register specif

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 621 of 1658 REJ09B0261-0100 (21) PCI Memory Bank Mask Register 2 (PCIMBMR2) This register

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 622 of 1658 REJ09B0261-0100 (22) PCI I/O Bank Register (PCIIOBR) This register specifies t

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 623 of 1658 REJ09B0261-0100 (23) PCI I/O Bank Mask Register (PCIIOBMR) This register is th

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 624 of 1658 REJ09B0261-0100 (24) PCI Cache Snoop Control Register 0 (PCICSCR0) An external

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 625 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 1, 0 SNPMD All 0

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 626 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 5 ⎯ All 0

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 627 of 1658 REJ09B0261-0100 (26) PCI Cache Snoop Address Register 0 (PCICSAR0) This regist

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 628 of 1658 REJ09B0261-0100 (27) PCI Cache Snoop Address Register 1 (PCICSAR1) This regist

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 629 of 1658 REJ09B0261-0100 (28) PCI PIO Data Register (PCIPDR) By reading or writing to t

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 36 of 1658 REJ09B0261-0100 (4) Floating-Point Status/Control Register (FPSCR) 31 30 29 28 27 26

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 630 of 1658 REJ09B0261-0100 13.4 Operation 13.4.1 Supported PCI Commands Table 13.4 Supp

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 631 of 1658 REJ09B0261-0100 13.4.2 PCIC Initialization After a power-on reset, the ENBL bi

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 632 of 1658 REJ09B0261-0100 13.4.3 Master Access This section describes how software contr

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 633 of 1658 REJ09B0261-0100 (2) Accessing PCI Memory Space Figure 13.2 shows the memory ma

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 634 of 1658 REJ09B0261-0100 For PCI memory space 0, the middle six bits ([23:18]) are contr

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 635 of 1658 REJ09B0261-0100 For PCI memory space 2 accesses, the middle eleven bits ([28:18

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 636 of 1658 REJ09B0261-0100 (3) Accessing PCI I/O Space Burst transfers are not supported

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 637 of 1658 REJ09B0261-0100 MSB31 0LSBSHwy dataPCI bus data1. Little endianA' B'

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 638 of 1658 REJ09B0261-0100 MSB31 0LSBSHwy dataPCI bus data1. Little endianA' B'

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 639 of 1658 REJ09B0261-0100 31 0A31 0A31 0A31 0AB B B BC C C CD D D DAB AB BA ABCD CD DC CD

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 37 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 17 to 12 Cause 000000

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 640 of 1658 REJ09B0261-0100 13.4.4 Target Access This section describes how the PCIC in th

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 641 of 1658 REJ09B0261-0100 To access the address space in this LSI, use PCIMBAR0/1, PCILSR

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 642 of 1658 REJ09B0261-0100 MBAREPCI address 31 28 20 0 29 19 PCIMBAR0/1 PCILSR0/1PCILAR0/

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 643 of 1658 REJ09B0261-0100 (3) Accessing PCIC Registers Configuration Registers: Configur

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 644 of 1658 REJ09B0261-0100 (6) Endian This LSI supports both the big and little endian fo

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 645 of 1658 REJ09B0261-0100 31MSB LSB0PCI bus dataSHwy data1. Little endianA' B'

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 646 of 1658 REJ09B0261-0100 31 0A31 0A31 0A31 0AB B B BC C C CD D D DAB AB BA ABCD CD DC CD

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 647 of 1658 REJ09B0261-0100 (7) Cache Coherency The PCIC supports cache coherency function

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 648 of 1658 REJ09B0261-0100 13.4.5 Host Mode (1) Operation in Host Mode The PCI interface

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 649 of 1658 REJ09B0261-0100 31 30 241623151110872 1 0 Configuration address registerPCI bus

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 38 of 1658 REJ09B0261-0100 <Big endian>DR (2i)FR (2i) FR (2i+1)8n+4 8n+78n 8n+363 063

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 650 of 1658 REJ09B0261-0100 Subsequently, after the PCIC requires the bus and transfer data

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 651 of 1658 REJ09B0261-0100 The PCIC can retain error information on the PCI bus. When an e

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 652 of 1658 REJ09B0261-0100 D0(Nomal state)D2(Clock stopped)D1(Bus idle)D3(Power-down) Figu

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 653 of 1658 REJ09B0261-0100 13.4.8 PCI Local Bus Basic Interface The PCI interface of this

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 654 of 1658 REJ09B0261-0100 PCICLK AD[31:0] PAR C/BE[3:0] PCIFRAMEIRDYDEVSELTRDYIDSELREQGNT

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 655 of 1658 REJ09B0261-0100 Addr D0AP DP0Com BE0D1DPn-1 DPnBE1 BEnDnPCICLK AD[31:0] PAR C/B

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 656 of 1658 REJ09B0261-0100 AddrD0APDP0Com BE0D1DPn-1DPn BE1BEnDnPCICLK AD[31:0] PAR C/BE[3

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 657 of 1658 REJ09B0261-0100 (2) Target Read/Write Cycle Timing The PCIC returns retries to

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 658 of 1658 REJ09B0261-0100 Addr D0APDP0Com BE0DisconnectConfiguration space accessLock PC

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 659 of 1658 REJ09B0261-0100 DP0Addr D0APCom BE0DisconnectConfiguration space accessLock PC

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 39 of 1658 REJ09B0261-0100 2.3 Memory-Mapped Registers Some control registers are mapped to the

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 660 of 1658 REJ09B0261-0100 Addr D0APDP0ComBE0DisconnectLockD1DPn-1DPn BE1 BEnDnPCICLK AD[3

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 661 of 1658 REJ09B0261-0100 Addr D0APDP0ComBE0DisconnectLockD1DPn-1DPn BE1 BEnDnPCICLK AD[3

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 662 of 1658 REJ09B0261-0100 (3) Address/Data Stepping Timing By writing 1 to the SC bit in

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 663 of 1658 REJ09B0261-0100 D1BE1PCICLK AD[31:0] PAR C/BE[3:0]PCIFRAMEIRDYDEVSELTRDYLegend:

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 664 of 1658 REJ09B0261-0100

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 665 of 1658 REJ09B0261-0100 Section 14 Direct Memory Access Controller (

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 666 of 1658 REJ09B0261-0100 Figure 14.1 shows a block diagram of the DMAC.

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 667 of 1658 REJ09B0261-0100 14.2 Input/Output Pins The DMAC-related exter

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 668 of 1658 REJ09B0261-0100 14.3 Register Descriptions Table 14.2 shows t

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 669 of 1658 REJ09B0261-0100 Channel Name Abbrev. R/W P4 Address Area 7 A

Rev.1.00 Jan. 10, 2008 Page vii of xxx REJ09B0261-0100 MSB Most Significant Bit PC Program Counter PCI Peripheral Component Interconnect PCIC PC

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 40 of 1658 REJ09B0261-0100 2.4 Data Formats in Registers Register operands are always longwords

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 670 of 1658 REJ09B0261-0100 Channel Name Abbrev. R/W P4 Address Area 7 A

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 671 of 1658 REJ09B0261-0100 Table 14.2 Register Configuration of the DMAC

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 672 of 1658 REJ09B0261-0100 Channel Name Abbrev. Power-on Reset by PRESET

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 673 of 1658 REJ09B0261-0100 Channel Name Abbrev. Power-on Reset by PRESET

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 674 of 1658 REJ09B0261-0100 Channel Name Abbrev. Power-on Reset by PRESET

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 675 of 1658 REJ09B0261-0100 14.3.1 DMA Source Address Registers 0 to 11 (

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 676 of 1658 REJ09B0261-0100 14.3.2 DMA Source Address Registers B0 to B3,

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 677 of 1658 REJ09B0261-0100 14.3.3 DMA Destination Address Registers 0 to

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 678 of 1658 REJ09B0261-0100 14.3.4 DMA Destination Address Registers B0 t

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 679 of 1658 REJ09B0261-0100 14.3.5 DMA Transfer Count Registers 0 to 11 (

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 41 of 1658 REJ09B0261-0100 Address AA707070703115 0 15 031 015 031 023 15 7 0A + 1 A + 2 A + 3By

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 680 of 1658 REJ09B0261-0100 14.3.6 DMA Transfer Count Registers B0 to B3,

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 681 of 1658 REJ09B0261-0100 14.3.7 DMA Channel Control Registers 0 to 11

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 682 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 27

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 683 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 21

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 684 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 19

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 685 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 17

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 686 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 15

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 687 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 11

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 688 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 2

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 689 of 1658 REJ09B0261-0100 14.3.8 DMA Operation Register 0, 1 (DMAOR0 an

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 42 of 1658 REJ09B0261-0100 From any statewhen reset/manualreset inputReset stateInstruction exec

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 690 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 11

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 691 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 2

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 692 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 0

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 693 of 1658 REJ09B0261-0100 14.3.9 DMA Extended Resource Selectors 0 to 5

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 694 of 1658 REJ09B0261-0100 • DMARS4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 695 of 1658 REJ09B0261-0100 • DMARS1 Bit Bit Name Initial Value R/W Des

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 696 of 1658 REJ09B0261-0100 • DMARS2 Bit Bit Name Initial Value R/W Des

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 697 of 1658 REJ09B0261-0100 • DMARS3 Bit Bit Name Initial Value R/W Des

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 698 of 1658 REJ09B0261-0100 • DMARS4 Bit Bit Name Initial Value R/W Des

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 699 of 1658 REJ09B0261-0100 • DMARS5 Bit Bit Name Initial Value R/W Des

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 43 of 1658 REJ09B0261-0100 2.7 Usage Notes 2.7.1 Notes on Self-Modifying Code To accelerate th

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 700 of 1658 REJ09B0261-0100 Table 14.3 List of Transfer Request Sources P

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 701 of 1658 REJ09B0261-0100 14.4 Operation When DMA transfer is requested

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 702 of 1658 REJ09B0261-0100 Choose whether DREQ is detected by edge or lev

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 703 of 1658 REJ09B0261-0100 (3) On-Chip Peripheral Module Request Mode On

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 704 of 1658 REJ09B0261-0100 Table 14.8 List of On-Chip Peripheral Module

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 705 of 1658 REJ09B0261-0100 CHCR DMARS RS[3:0] MID RIDDMA Transfer Reques

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 706 of 1658 REJ09B0261-0100 14.4.2 Channel Priority When the DMAC receive

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 707 of 1658 REJ09B0261-0100 CH1 > CH2 > CH3 > CH4 > CH5 > C

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 708 of 1658 REJ09B0261-0100 Figure 14.3 shows how the priority changes whe

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 709 of 1658 REJ09B0261-0100 14.4.3 DMA Transfer Types Tables 14.9 and 14.

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 44 of 1658 REJ09B0261-0100

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 710 of 1658 REJ09B0261-0100 Table 14.10 DMA Transfer Directions for On-Ch

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 711 of 1658 REJ09B0261-0100 (1) Dual Address Mode In dual address mode, b

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 712 of 1658 REJ09B0261-0100 Transfer source addressTransfer destination ad

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 713 of 1658 REJ09B0261-0100 (2) Bus Modes Bus modes include cycle steal m

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 714 of 1658 REJ09B0261-0100 • Intermittent mode 16 (DMAOR. CMS = 10, CHCR

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 715 of 1658 REJ09B0261-0100 SuperHywaybus cycleRead Write Read Write Read

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 716 of 1658 REJ09B0261-0100 DMA CH0Cycle stealCH0 transfer source(a) CH0:

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 717 of 1658 REJ09B0261-0100 14.4.4 DMA Transfer Flow After intended trans

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 718 of 1658 REJ09B0261-0100 Notes: 1. In repeat mode, a transfer reques

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 719 of 1658 REJ09B0261-0100 14.4.5 Repeat Mode Transfer A repeat mode tra

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 45 of 1658 REJ09B0261-0100 Section 3 Instruction Set This LSI's instruction set is implemen

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 720 of 1658 REJ09B0261-0100 This function enables sequential voice compres

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 721 of 1658 REJ09B0261-0100 14.4.7 DREQ Pin Sampling Timing Figures 14.13

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 722 of 1658 REJ09B0261-0100 : Non-sensitive periodCLKOUTBus cycleDREQ (R

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 723 of 1658 REJ09B0261-0100 CLKOUTBus cycleDREQ(Overrun 0, High level)DRAK

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 724 of 1658 REJ09B0261-0100 Bus cycleDREQ(Overrun 0, High level)DRAK (High

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 725 of 1658 REJ09B0261-0100 Acceptance startedAccepted after one cycle of

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 726 of 1658 REJ09B0261-0100 Bus cycle(Overrun 0, High level)DRAK (High-act

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 727 of 1658 REJ09B0261-0100 Acceptance startedAccepted after one cycle of

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 728 of 1658 REJ09B0261-0100 Acceptance startedAccepted after one cycle of

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 729 of 1658 REJ09B0261-0100 14.5 DMAC Interrupt Sources In the DMAC, each

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 46 of 1658 REJ09B0261-0100 Table 3.1 Execution Order of Delayed Branch Instructions Instructions

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 730 of 1658 REJ09B0261-0100 14.6 Usage Notes Note the following things in

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 731 of 1658 REJ09B0261-0100 14.6.6 DACK/DREQ Setting If the IWRRD, IWRRS,

14. Direct Memory Access Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 732 of 1658 REJ09B0261-0100

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 733 of 1658 REJ09B0261-0100 Section 15 Clock Pulse Generator (CPG) The CPG generate

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 734 of 1658 REJ09B0261-0100 Oscillator circuitControl sectionCrystal oscillator circu

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 735 of 1658 REJ09B0261-0100 The function of each block in the CPG is as follows. • P

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 736 of 1658 REJ09B0261-0100 15.2 Input/Output Pins Table 15.1 shows the CPG pin conf

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 737 of 1658 REJ09B0261-0100 15.3 Clock Operating Modes Table 15.2 shows the relation

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 738 of 1658 REJ09B0261-0100 Table 15.3 Clock Operating Modes and Frequency Multiplic

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 739 of 1658 REJ09B0261-0100 15.4 Register Descriptions Table 15.5 lists the register

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 47 of 1658 REJ09B0261-0100 3.2 Addressing Modes Addressing modes and effective address calculatio

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 740 of 1658 REJ09B0261-0100 Table 15.6 Register State in Each Processing Mode Regist

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 741 of 1658 REJ09B0261-0100 15.4.1 Frequency Control Register 0 (FRQCR0) FRQCR0 is a

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 742 of 1658 REJ09B0261-0100 15.4.2 Frequency Control Register 1 (FRQCR1) FRQCR1 is a

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 743 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 30 29 28 I

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 744 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 11 10 9 8 S2F

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 745 of 1658 REJ09B0261-0100 15.4.3 Frequency Display Register 1 (FRQMR1) FRQMR1 is a

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 746 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 19 18 17 16 B

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 747 of 1658 REJ09B0261-0100 15.4.4 PLL Control Register (PLLCR) PLLCR is a 32-bit re

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 748 of 1658 REJ09B0261-0100 15.5 Calculating the Frequency Table 15.7 shows the rela

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 749 of 1658 REJ09B0261-0100 15.6 How to Change the Frequency To change the frequency

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 48 of 1658 REJ09B0261-0100 Addressing Mode Instruction Format Effective Address Calculation Metho

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 750 of 1658 REJ09B0261-0100 4. Set H'CF000001 in FRQCR0 to enable execution of

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 751 of 1658 REJ09B0261-0100 Table 15.8 Selectable Combinations of Clock Frequency (C

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 752 of 1658 REJ09B0261-0100 Division ratio of divider 2 FRQMR1 read value CPU clock

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 753 of 1658 REJ09B0261-0100 Division ratio of divider 2 FRQMR1 read value CPU clock I

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 754 of 1658 REJ09B0261-0100 Table 15.10 Selectable Combinations of Clock Frequency (

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 755 of 1658 REJ09B0261-0100 Table 15.11 Selectable Combinations of Clock Frequency (

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 756 of 1658 REJ09B0261-0100 15.7 Notes on Designing Board 1. Note on Using a Crysta

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 757 of 1658 REJ09B0261-0100 CB1RCB1CPB1CB2RCB2CPB2CB3RCB3CPB3CB4RCB4CPB4CB5RCB5CPB5Po

15. Clock Pulse Generator (CPG) Rev.1.00 Jan. 10, 2008 Page 758 of 1658 REJ09B0261-0100

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 759 of 1658 REJ09B0261-0100 Section 16 Watchdog Timer and Reset (WDT) The watchd

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 49 of 1658 REJ09B0261-0100 Addressing Mode Instruction Format Effective Address Calculation Metho

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 760 of 1658 REJ09B0261-0100 Figure 16.1 is a block diagram of the WDT. PRESETMRESE

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 761 of 1658 REJ09B0261-0100 16.2 Input/Output Pins Table 16.1 shows the pin confi

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 762 of 1658 REJ09B0261-0100 16.3 Register Descriptions Table 16.2 shows the regis

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 763 of 1658 REJ09B0261-0100 16.3.1 Watchdog Timer Stop Time Register (WDTST) WDTS

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 764 of 1658 REJ09B0261-0100 16.3.2 Watchdog Timer Control/Status Register (WDTCSR

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 765 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 RSTS 0 R

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 766 of 1658 REJ09B0261-0100 16.3.3 Watchdog Timer Base Stop Time Register (WDTBST

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 767 of 1658 REJ09B0261-0100 16.3.4 Watchdog Timer Counter (WDTCNT) WDTCNT is a 32

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 768 of 1658 REJ09B0261-0100 16.3.5 Watchdog Timer Base Counter (WDTBCNT) WDTBCNT

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 769 of 1658 REJ09B0261-0100 16.4 Operation 16.4.1 Reset Request Power-on reset a

Rev.1.00 Jan. 10, 2008 Page viii of xxx REJ09B0261-0100 All trademarks and registered trademarks are the property of their respective owners.

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 50 of 1658 REJ09B0261-0100 Addressing Mode Instruction Format Effective Address Calculation Metho

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 770 of 1658 REJ09B0261-0100 (2) Manual Reset • Requesting sources ⎯ A general e

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 771 of 1658 REJ09B0261-0100 16.4.2 Using Watchdog Timer Mode 1. Set the WDTCNT o

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 772 of 1658 REJ09B0261-0100 16.4.4 Time until WDT Counters Overflow The relations

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 773 of 1658 REJ09B0261-0100 WDTBCNT is an 18-bit counter that is incremented by th

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 774 of 1658 REJ09B0261-0100 16.5 Status Pin Change Timing during Reset 16.5.1 Po

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 775 of 1658 REJ09B0261-0100 (2) Power-On Reset Caused by PRESET Input during Norm

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 776 of 1658 REJ09B0261-0100 (3) Power-On Reset Caused by PRESET Input in Sleep Mo

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 777 of 1658 REJ09B0261-0100 16.5.2 Power-On Reset by Watchdog Timer Overflow The

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 778 of 1658 REJ09B0261-0100 (2) Power-On Reset Caused by Watchdog Timer Overflow

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 779 of 1658 REJ09B0261-0100 16.5.3 Manual Reset by Watchdog Timer Overflow The ti

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 51 of 1658 REJ09B0261-0100 Addressing Mode Instruction Format Effective Address Calculation Metho

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 780 of 1658 REJ09B0261-0100 (2) Manual Reset Caused by Watchdog Timer Overflow in

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 781 of 1658 REJ09B0261-0100 Section 17 Power-Down Mode In power-down mode, some of the on-chip

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 782 of 1658 REJ09B0261-0100 Table 17.1 States of Power-Down Modes State On-Chip Peripheral Modul

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 783 of 1658 REJ09B0261-0100 17.2 Input/Output Pins Table 17.2 shows the pins related to power-do

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 784 of 1658 REJ09B0261-0100 Table 17.4 Register States of CPG in Each Processing Mode Power-on R

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 785 of 1658 REJ09B0261-0100 17.3.1 Sleep Control Register (SLPCR) SLPCR is a 32-bit readable/wri

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 786 of 1658 REJ09B0261-0100 17.3.2 Standby Control Register 0 (MSTPCR0) MSTPCR0 is a 32-bit read

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 787 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 21, 20 MSTP[21:20] All 0

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 788 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 9, 8 MSTP[9:8] All 0 R/

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 789 of 1658 REJ09B0261-0100 17.3.3 Standby Control Register 1 (MSTPCR1) MSTPCR1 is a 32-bit read

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 52 of 1658 REJ09B0261-0100 3.3 Instruction Set Table 3.3 shows the notation used in the SH instru

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 790 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 16 to 6 ⎯ All 0 R/W R

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 791 of 1658 REJ09B0261-0100 17.3.4 Standby Display Register (MSTPMR) MSTPMR is a 32-bit readable

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 792 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5, 4 MSTPS105 MSTPS104 A

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 793 of 1658 REJ09B0261-0100 17.4 Sleep Mode 17.4.1 Transition to Sleep Mode When the SLEEP inst

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 794 of 1658 REJ09B0261-0100 17.5 Deep Sleep Mode 17.5.1 Transition to Deep Sleep Mode If a SLE

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 795 of 1658 REJ09B0261-0100 17.5.2 Releasing Deep Sleep Mode Deep sleep mode is released by mean

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 796 of 1658 REJ09B0261-0100 17.6 Module Standby Functions This LSI supports the module standby s

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 797 of 1658 REJ09B0261-0100 17.7 Timing of the Changes on the STATUS Pins 17.7.1 Reset For deta

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 798 of 1658 REJ09B0261-0100

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 799 of 1658 REJ09B0261-0100 Section 18 Timer Unit (TMU) This LSI includes an on-chip 32-bit ti

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 53 of 1658 REJ09B0261-0100 Item Format Description Privileged mode "Privileged" mean

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 800 of 1658 REJ09B0261-0100 Figure 18.1 shows a block diagram of the TMU. Channel 0, 1Channel 2C

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 801 of 1658 REJ09B0261-0100 18.2 Input/Output Pins Table 18.1 shows the TMU pin configuration.

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 802 of 1658 REJ09B0261-0100 18.3 Register Descriptions Tables 18.2 and 18.3 show the TMU regist

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 803 of 1658 REJ09B0261-0100 Table 18.3 Register Configuration (2) Channel Register Name Abbrev

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 804 of 1658 REJ09B0261-0100 18.3.1 Timer Start Registers (TSTRn) (n = 0, 1) The TSTR registers

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 805 of 1658 REJ09B0261-0100 • TSTR1 0123456700000000STR3STR4STR5—————R/WR/WR/WRRRRRBIt:Initial

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 806 of 1658 REJ09B0261-0100 18.3.2 Timer Constant Registers (TCORn) (n = 0 to 5) The TCOR regis

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 807 of 1658 REJ09B0261-0100 18.3.4 Timer Control Registers (TCRn) (n = 0 to 5) The TCR register

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 808 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7 6 ICPE1*1 ICPE0*1 0 0

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 809 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 1 0 TPSC2 TPSC1 TPSC0

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 54 of 1658 REJ09B0261-0100 Instruction Operation Instruction Code Privileged T Bit New MOV.B

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 810 of 1658 REJ09B0261-0100 18.4 Operation Each channel has a 32-bit timer counter (TCNT) and a

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 811 of 1658 REJ09B0261-0100 (2) Auto-Reload Count Operation Figure 18.3 shows the TCNT auto-rel

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 812 of 1658 REJ09B0261-0100 (3) TCNT Count Timing • Operating on internal clock Any of five in

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 813 of 1658 REJ09B0261-0100 18.4.2 Input Capture Function Channel 2 has an input capture functi

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 814 of 1658 REJ09B0261-0100 18.5 Interrupts There are seven TMU interrupt sources: underflow in

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 815 of 1658 REJ09B0261-0100 18.6 Usage Notes 18.6.1 Register Writes When writing to a TMU regi

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 816 of 1658 REJ09B0261-0100

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 817 of 1658 REJ09B0261-0100 Section 19 Display Unit (DU) 19.1 Features The display unit (DU)

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 818 of 1658 REJ09B0261-0100 CRT Scan Mode (CRT Scan Method): Internal register settings can be

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 819 of 1658 REJ09B0261-0100 Figure 19.1 shows a block diagram of the display unit (DU). Pin con

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 55 of 1658 REJ09B0261-0100 Instruction Operation Instruction Code Privileged T Bit New MOVT

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 820 of 1658 REJ09B0261-0100 19.2 Input/Output Pins Table 19.1 shows the pin configuration of t

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 821 of 1658 REJ09B0261-0100 Pin Name Number I/O Function Signal Name Used in This Section DG

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 822 of 1658 REJ09B0261-0100 • Display mode register (DSMR) ⎯ VSPM bit (VSYNC pin mode) ⎯ OD

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 823 of 1658 REJ09B0261-0100 Table 19.2 Register Configuration Register Name Abbr. R/W P4 Ad

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 824 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchrono

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 825 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchrono

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 826 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchrono

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 827 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchrono

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 828 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchrono

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 829 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchrono

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 56 of 1658 REJ09B0261-0100 Instruction Operation Instruction Code Privileged T Bit New CMP/STR

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 830 of 1658 REJ09B0261-0100 Table 19.3 Status of Registers in Each Processing Mode Register Na

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 831 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manua

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 832 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manua

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 833 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manua

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 834 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manua

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 835 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manua

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 836 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manua

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 837 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manua

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 838 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manua

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 839 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manua

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 57 of 1658 REJ09B0261-0100 Instruction Operation Instruction Code Privileged T Bit New MULU.W

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 840 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manua

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 841 of 1658 REJ09B0261-0100 19.3.1 Display Unit System Control Register The display unit syste

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 842 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 16 IUPD

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 843 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9 DRES 1

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 844 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 7, 6 TV

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 845 of 1658 REJ09B0261-0100 19.3.2 Display Mode Register (DSMR) The display mode register (DSM

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 846 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 24 CSPM

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 847 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 14, 13

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 848 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 7, 6 CS

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 849 of 1658 REJ09B0261-0100 19.3.3 Display Status Register (DSSR) The display status register

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 58 of 1658 REJ09B0261-0100 Instruction Operation Instruction Code Privileged T Bit New XOR #im

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 850 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 20 DFB5

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 851 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 16 DFB1

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 852 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 13, 12

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 853 of 1658 REJ09B0261-0100 19.3.4 Display Unit Status Register Clear Register (DSRCR) The dis

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 854 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9 RICL

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 855 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 31 to 16

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 856 of 1658 REJ09B0261-0100 The following are conditions, based on DSSR and this register, for

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 857 of 1658 REJ09B0261-0100 19.3.6 Color Palette Control Register (CPCR) The color palette con

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 858 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 18 CP3C

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 859 of 1658 REJ09B0261-0100 19.3.7 Display Plane Priority Register (DPPR) The display plane pr

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 59 of 1658 REJ09B0261-0100 Table 3.8 Branch Instructions Instruction Operation Instruction Cod

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 860 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 19 DPE5

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 861 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 11 DPE3

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 862 of 1658 REJ09B0261-0100 19.3.8 Display Unit Extensional Function Enable Register (DEFR) Th

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 863 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 4 ABRE

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 864 of 1658 REJ09B0261-0100 19.3.9 Horizontal Display Start Register (HDSR) The horizontal dis

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 865 of 1658 REJ09B0261-0100 19.3.10 Horizontal Display End Register (HDER) The horizontal disp

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 866 of 1658 REJ09B0261-0100 19.3.11 Vertical Display Start Register (VDSR) The vertical displa

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 867 of 1658 REJ09B0261-0100 19.3.12 Vertical Display End Register (VDER) The vertical display

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 868 of 1658 REJ09B0261-0100 19.3.13 Horizontal Cycle Register (HCR) The horizontal cycle regis

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 869 of 1658 REJ09B0261-0100 19.3.14 Horizontal Sync Width Register (HSWR) The horizontal sync

Rev.1.00 Jan. 10, 2008 Page ix of xxx REJ09B0261-0100 Contents Section 1 Overview...

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 60 of 1658 REJ09B0261-0100 Instruction Operation Instruction Code Privileged T Bit New LDC Rm,

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 870 of 1658 REJ09B0261-0100 19.3.15 Vertical Cycle Register (VCR) The vertical cycle register

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 871 of 1658 REJ09B0261-0100 19.3.16 Vertical Sync Point Register (VSPR) The vertical sync poin

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 872 of 1658 REJ09B0261-0100 19.3.17 Equal Pulse Width Register (EQWR) The equal pulse width re

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 873 of 1658 REJ09B0261-0100 19.3.18 Separation Width Register (SPWR) The separation width regi

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 874 of 1658 REJ09B0261-0100 19.3.19 CLAMP Signal Start Register (CLAMPSR) The CLAMP signal sta

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 875 of 1658 REJ09B0261-0100 19.3.20 CLAMP Signal Width Register (CLAMPWR) The CLAMP signal wid

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 876 of 1658 REJ09B0261-0100 19.3.21 DE Signal Start Register (DESR) The DE signal start regist

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 877 of 1658 REJ09B0261-0100 19.3.22 DE Signal Width Register (DEWR) The DE signal width regist

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 878 of 1658 REJ09B0261-0100 19.3.23 Color Palette 1 Transparent Color Register (CP1TR) The col

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 879 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 12 CP1I

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 61 of 1658 REJ09B0261-0100 Instruction Operation Instruction Code Privileged T Bit New SETS

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 880 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 5 CP1I5

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 881 of 1658 REJ09B0261-0100 19.3.24 Color Palette 2 Transparent Color Register (CP2TR) The col

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 882 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 12 CP2I

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 883 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 5 CP2I5

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 884 of 1658 REJ09B0261-0100 19.3.25 Color Palette 3 Transparent Color Register (CP3TR) The col

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 885 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 12 CP3I

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 886 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 5 CP3I5

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 887 of 1658 REJ09B0261-0100 19.3.26 Color Palette 4 Transparent Color Register (CP4TR) The col

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 888 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 12 CP4I

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 889 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 5 CP4I5

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 62 of 1658 REJ09B0261-0100 Instruction Operation Instruction Code Privileged T Bit New SYNCO

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 890 of 1658 REJ09B0261-0100 19.3.27 Display Off Mode Output Register (DOOR) The display off mo

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 891 of 1658 REJ09B0261-0100 19.3.28 Color Detection Register (CDER) The color detection regist

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 892 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 1, 0 ⎯

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 893 of 1658 REJ09B0261-0100 Bit Bit NameInitial Value R/W Internal Update Description 9, 8 ⎯ A

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 894 of 1658 REJ09B0261-0100 19.3.30 Raster Interrupt Offset Register (RINTOFSR) The raster int

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 895 of 1658 REJ09B0261-0100 19.3.31 Plane n Mode Register (PnMR) (n = 1 to 6) The plane n mode

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 896 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 14 to 12

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 897 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9, 8 Pn

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 898 of 1658 REJ09B0261-0100 19.3.32 Plane n Memory Width Register (PnMWR) (n = 1 to 6) The pla

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 899 of 1658 REJ09B0261-0100 19.3.33 Plane n Blending Ratio Register (PnALPHAR) (n = 1 to 6) Th

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 63 of 1658 REJ09B0261-0100 Instruction Operation Instruction Code Privileged T Bit NewFADD

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 900 of 1658 REJ09B0261-0100 Bit Bit NameInitial Value R/W Internal Update Description Plane n B

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 901 of 1658 REJ09B0261-0100 Bit Bit NameInitial Value R/W Internal Update Description 7 to 0 Pn

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 902 of 1658 REJ09B0261-0100 19.3.35 Plane n Display Size Y Register (PnDSYR) (n = 1 to 6) The

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 903 of 1658 REJ09B0261-0100 19.3.36 Plane n Display Position X Register (PnDPXR) (n = 1 to 6)

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 904 of 1658 REJ09B0261-0100 19.3.37 Plane n Display Position Y Register (PnDPYR) (n = 1 to 6)

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 905 of 1658 REJ09B0261-0100 19.3.38 Plane n Display Area Start Address 0 Register (PnDSA0R) (n

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 906 of 1658 REJ09B0261-0100 19.3.39 Plane n Display Area Start Address 1 Register (PnDSA1R) (n

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 907 of 1658 REJ09B0261-0100 19.3.40 Plane n Start Position X Register (PnSPXR) (n = 1 to 6) Th

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 908 of 1658 REJ09B0261-0100 19.3.41 Plane n Start Position Y Register (PnSPYR) (n = 1 to 6) Th

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 909 of 1658 REJ09B0261-0100 19.3.42 Plane n Wrap Around Start Position Register (PnWASPR) (n =

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 64 of 1658 REJ09B0261-0100 Table 3.12 Floating-Point Control Instructions Instruction Operation

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 910 of 1658 REJ09B0261-0100 19.3.43 Plane n Wrap Around Memory Width Register (PnWAMWR) (n = 1

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 911 of 1658 REJ09B0261-0100 19.3.44 Plane n Blinking Time Register (PnBTR) (n = 1 to 6) The pl

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 912 of 1658 REJ09B0261-0100 19.3.45 Plane n Transparent Color 1 Register (PnTC1R) (n = 1 to 6)

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 913 of 1658 REJ09B0261-0100 19.3.46 Plane n Transparent Color 2 Register (PnTC2R) (n = 1 to 6)

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 914 of 1658 REJ09B0261-0100 19.3.47 Plane n Memory Length Register (PnMLR) (n = 1 to 6) The pl

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 915 of 1658 REJ09B0261-0100 19.3.48 Color Palette 1 Register 000 to 255 (CP1_000R to CP1_255R)

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 916 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9, 8 ⎯

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 917 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 31 to 24

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 918 of 1658 REJ09B0261-0100 19.3.50 Color Palette 3 Register 000 to 255 (CP3_000R to CP3_255R)

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 919 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9, 8 ⎯

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 65 of 1658 REJ09B0261-0100 Section 4 Pipelining This LSI is a 2-ILP (instruction-level-parallelism) s

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 920 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 31 to 24

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 921 of 1658 REJ09B0261-0100 19.3.52 External Synchronization Control Register (ESCR) The exte

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 922 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 4 to 0

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 923 of 1658 REJ09B0261-0100 19.3.53 Output Signal Timing Adjustment Register (OTAR) The outpu

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 924 of 1658 REJ09B0261-0100 Bit Bit NameInitial Value R/W Internal Update Description 30 to 28

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 925 of 1658 REJ09B0261-0100 Bit Bit NameInitial Value R/W Internal Update Description 26 to 24

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 926 of 1658 REJ09B0261-0100 Bit Bit NameInitial Value R/W Internal Update Description 22 to 20

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 927 of 1658 REJ09B0261-0100 Bit Bit NameInitial Value R/W Internal Update Description 10 to 8

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 928 of 1658 REJ09B0261-0100 Bit Bit NameInitial Value R/W Internal Update Description 6 to 4 D

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 929 of 1658 REJ09B0261-0100 Bit Bit NameInitial Value R/W Internal Update Description 2 to 0 S

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 66 of 1658 REJ09B0261-0100 Figure 4.2 shows the instruction execution patterns. Representations in figu

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 930 of 1658 REJ09B0261-0100 19.4 Operation 19.4.1 Configuration of Output Screen The display

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 931 of 1658 REJ09B0261-0100 Table 19.4 Display Functions of Planes Display Data Format Displa

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 932 of 1658 REJ09B0261-0100 Frame buffer 2A double-buffer function is used to switch the frame

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 933 of 1658 REJ09B0261-0100 19.4.2 Display On/Off All plane display can be turned on and off u

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 934 of 1658 REJ09B0261-0100 19.4.3 Plane Parameter For each plane, a display area start positi

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 935 of 1658 REJ09B0261-0100 Table 19.6 Memory Parameter/ Monitor Parameter Setting Registers N

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 936 of 1658 REJ09B0261-0100 19.4.4 Memory Allocation A display start address for the display s

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 937 of 1658 REJ09B0261-0100 19.4.5 Input Display Data Format The following format is used for

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 938 of 1658 REJ09B0261-0100 • 16 bit/pixel: ARGB The ARGB levels are represented using A:1, R:

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 939 of 1658 REJ09B0261-0100 • UYVY format A+3 A+2 A+1 A A A+1 A+2 A+3 31 23 15 7

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 67 of 1658 REJ09B0261-0100 I1 I2 I3(I1) (ID)ID E1/S1 E2/s2 E3/s3 WBI3I3I3(I2)(I3)I1 I2 ID E1/S1 E2/S2 E

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 940 of 1658 REJ09B0261-0100 19.4.6 Output Data Format When outputting digital RGB data from th

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 941 of 1658 REJ09B0261-0100 Endian conversion in each of the units indicated below is shown in

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 942 of 1658 REJ09B0261-0100 19.4.8 Color Palettes 8 bits/pixel data employs color palettes. Fo

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 943 of 1658 REJ09B0261-0100 19.4.9 Superpositioning of Planes For each plane, three types of c

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 944 of 1658 REJ09B0261-0100 Table 19.11 RGB888 Bit Configuration in Each Display Data Format D

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 945 of 1658 REJ09B0261-0100 When the PnDDF bit in PnMR is set to ARGB, and moreover the PnSPIM

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 946 of 1658 REJ09B0261-0100 Table 19.12 Transparent Color Specification Registers Data Format

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 947 of 1658 REJ09B0261-0100 19.4.10 Display Contention Color Palette Contention: When performi

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 948 of 1658 REJ09B0261-0100 P1 P1 P2 P3ΔΔΔX XP2 ΔΔX ΔXP3 Δ X ΔΔXP1P1P1P1P2P2P3BPORP1P1P1αP3P1

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 949 of 1658 REJ09B0261-0100 Plane Priority Order: The display priority order for planes is set

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 68 of 1658 REJ09B0261-0100 I3I3I3I1 I2 IDs1 s2 s3WBI1 I2 IDWBI1 I2 ID E1/S1 E2/s2 E3/s3E1/s1 E2/s2 E3/S

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 950 of 1658 REJ09B0261-0100 19.4.12 Scroll Display By setting display area and display screen

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 951 of 1658 REJ09B0261-0100 19.4.13 Wraparound Display In addition to display scrolling, wrap-

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 952 of 1658 REJ09B0261-0100 19.4.14 Upper-Left Overflow Display For each plane, a display star

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 953 of 1658 REJ09B0261-0100 19.4.15 Double Buffer Control The double buffer control of the dis

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 954 of 1658 REJ09B0261-0100 19.4.16 Sync Mode In order to facilitate synchronization with exte

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 955 of 1658 REJ09B0261-0100 TV (sync signal generation circuit): MasterClockHSYNC VSYNCR,G,BTh

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 956 of 1658 REJ09B0261-0100 19.5 Display Control 19.5.1 Display Timing Generation In the disp

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 957 of 1658 REJ09B0261-0100 Table 19.13 Variables Defined in Display Screen Variables Contents

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 958 of 1658 REJ09B0261-0100 Table 19.14 Correspondence Table of Settings of Display Timing Gen

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 959 of 1658 REJ09B0261-0100 19.5.2 CSYNC When in master mode, a CSYNC (composite sync) signal

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 69 of 1658 REJ09B0261-0100 I1 I2 I3 ID S1 S2 S3 WBI3I3I3I3I1 I2 ID S1 S2 S3WBI1 I2 ID S1 S2 S3WBE2S2 E3

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 960 of 1658 REJ09B0261-0100 VSYNC CSYNC (CSY = 00) EQW (CSY = 10) (CSY = 11) 1/2HC 1/2HC SPWHSW

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 961 of 1658 REJ09B0261-0100 19.5.3 Scan Method The scan method can be selected from among non

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 962 of 1658 REJ09B0261-0100 Raster scanned in an odd fieldRaster scanned in an even fie

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 963 of 1658 REJ09B0261-0100 • Example of vertical scan period Non-interlaced mode: 1/60 seco

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 964 of 1658 REJ09B0261-0100 • Display in interlaced method At every scan period VC of the inpu

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 965 of 1658 REJ09B0261-0100 19.5.4 Color Detection When output display data matches a color se

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 966 of 1658 REJ09B0261-0100 19.5.5 Output Signal Timing Adjustment The display unit (DU) enabl

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 967 of 1658 REJ09B0261-0100 19.5.6 CLAMP Signal and DE Signal The display unit (DU) generates

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 968 of 1658 REJ09B0261-0100 19.6 Power-Down Sequence When executing the power-down sequence by

20. Graphics Data Translation Accelerator (GDTA) Rev.1.00 Jan. 10, 2008 Page 969 of 1658 REJ09B0261-0100 Section 20 Graphics Data Translation A