Renesas PCA7401 Informacje Techniczne Pobierz pdf (Strona 41)

MITSUBISHI MICROCOMPUTERS

M37270MF-XXXSP

M37270EF-XXXSP, M37270EFSP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

Table 7. Set values of I

C clock control register and SCL

frequency

(4) I

C Control Register

The I

C control register (address 00F916) controls data communica-

tion format.

■ Bits 0 to 2: Bit counter (BC0–BC2)

These bits decide the number of bits for the next 1-byte data to be

transmitted. An interrupt request signal occurs immediately after the

number of bits specified with these bits are transmitted.

When a START condition is received, these bits become “000

2” and

the address data is always transmitted and received in 8 bits.

■ Bit 3: I

C interface use enable bit (ES0)

This bit enables to use the multimaster I

C BUS interface. When this

bit is set to “0,” the use disable status is provided, so the SDA and

the SCL become high-impedance. When the bit is set to “1,” use of

the interface is enabled.

When ES0 = “0,” the following is performed.

•

PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I

status register at address 00F8

16 ).

•

Writing data to the I

C data shift register (address 00F616) is dis-

abled.

■ Bit 4: Data format selection bit (ALS)

This bit decides whether or not to recognize slave addresses. When

this bit is set to “0,” the addressing format is selected, so that ad-

dress data is recognized. When a match is found between a slave

address and address data as a result of comparison or when a gen-

eral call (refer to “(5) I

C Status Register,” bit 1) is received, trans-

mission processing can be performed. When this bit is set to “1,” the

free data format is selected, so that slave addresses are not recog-

nized.

■ Bit 5: Addressing format selection bit (10BIT SAD)

This bit selects a slave address specification format. When this bit is

set to “0,” the 7-bit addressing format is selected. In this case, only

the high-order 7 bits (slave address) of the I

C address register (ad-

dress 00F7

16) are compared with address data. When this bit is set

to “1,” the 10-bit addressing format is selected, all the bits of the I

address register are compared with address data.

■ Bits 6 and 7: Connection control bits between I

C-BUS interface

and ports (BSEL0, BSEL1)

These bits controls the connection between SCL and ports or SDA

and ports (refer to Figure 39).

Fig. 38. Structure of I

C clock control register

ACK

BIT

FAST

MODE

CCR4 CCR3 CCR2 CCR1 CCR0

C clock control register

(S2 : address 00FA

16)

SCL frequency

control bits

Refer to Table 7.

SCL mode

specification bit

0 : Standard clock

mode

1 : High-speed clock

mode

ACK bit

0 : ACK is returned.

1 : ACK is not returned.

ACK clock bit

0 : No ACK clock

1 : ACK clock

Setting value of

CCR4–CCR0

Standard clock

mode

Setting disabled

100

83.3

500/CCR value

17.2

16.6

16.1

High-speed clock

mode

Setting disabled

333

250

400(Note)

166

1000/CCR value

34.5

33.3

32.3

CCR4

CCR3

CCR2

CCR1

CCR0

Note: At 400 kHz in the high-speed clock mode, the duty is 40%.

In the other cases, the duty is 50%.

…

SCL frequency

(at φ = 4MHz, unit : kHz)

1 2 ... 36 37 38 39 40 41 42 43 44 45 46 ... 96 97

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